Search Results - Theory of computation → Approximation algorithms analysis

Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis by Gamaarachchi, Hasindu, Liyanage, Kisaru, Parameswaran, Sri

“…; and three, novel algorithms and domain-specific architectures for rapid in situ analysis of third-generation sequencing data…”
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A Universal Method for Task Allocation on FP-FPS Multiprocessor Systems with Spin Locks by Zhao, Shuai, Chen, Nan, Fang, Yinjie, Li, Zhao, Chang, Wanli

“… Unfortunately, these existing methods either are tailored for specific scheduling and analysis approaches, or introduce runtime overhead that undermines their applicability…”
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Optimal Memory Allocation and Scheduling for DMA Data Transfers under the LET Paradigm by Pazzaglia, Paolo, Casini, Daniel, Biondi, Alessandro, Natale, Marco Di

“…The Logical Execution Time (LET) paradigm is increasingly used to achieve predictable communications in modern multicore automotive applications. Direct Memory…”
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BLESS: Bandwidth and Locality Enhanced SMEM Seeding Acceleration for DNA Sequencing by Han, Seunghee, Moon, Seungjae, Suh, Teokkyu, Heo, JaeHoon, Kim, Joo-Young

“… The seeding process, which aims to find locations of super-maximal exact matches (SMEM) between the DNA samples and reference genome for comparative analysis, has emerged as a major bottleneck due to its memory-intensive characteristics…”
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Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism by Liu, Genggeng, Huang, Pengcheng, Li, Zepeng, Liu, Wen-Hao, Huang, Xing, Guo, Wenzhong

“… Based on the independence and divisibility of track assignment, we propose a GPU-accelerated parallel track assignment algorithm…”
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Cost-Distance Steiner Trees for Timing-Constrained Global Routing by Held, Stephan, Perner, Edgar

“… We also prove that our algorithm guarantees an approximation factor of \mathcal{O}(\log t). This matches the best…”
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Dynamic Local Usage: An Accurate Model for Usage of Tile-Internal Wiring in Global Routing by Bihler, Tilmann, Blankenburg, Daniel

“… Key innovations include tip-to-tip penalty extensions to accurately model packing density and new algorithms to optimize routes according to the DLU congestion model…”
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TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell Methodology by Hsu, Chen-Hao, Pan, David Z., Perron, Laurent, Didier, Frederic, Xu, Xiaoqing, Chen, Hao

“…In advanced technology nodes, benefits from scaling have become limited in terms of power, performance, and area (PPA), necessitating improvements through…”
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Any-Angle Routing for Redistribution Layers in 2.5D IC Packages by Chung, Min-Hsuan, Chuang, Je-Wei, Chang, Yao-Wen

“… This paper proposes the first any-angle routing algorithm in the literature for multiple RDLs…”
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Placement Tomography-Based Routing Blockage Generation for DRV Hotspot Mitigation by Kahng, Andrew B., Kundu, Sayak, Yoon, Dooseok

“…A fundamental goal in modern physical design is for the post-route layout to have a fixable number of remaining design rule violations (DRVs). We study how to…”
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Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints by Liu, Qinghai, Tang, Qinfei, Chen, Jiarui, Chen, Chuandong, Zhu, Ziran, He, Huan, Chen, Jianli, Chang, Yao-Wen

“…PCB routing becomes time-consuming as the complexity of PCB design increases. Unlike traditional schemes that treat the two essential PCB routing processes…”
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RippleFPGA: A routability-driven placement for large-scale heterogeneous FPGAs by Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Young, Evangeline F. Y., Bei Yu

“… In this paper, we propose a routability-driven placement algorithm for large-scale heterogeneous FPGAs…”
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Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures by Chen, Yen-Ting, Chang, Yao-Wen

“…In advanced packages, redistribution layers (RDLs) are extra metal layers for high interconnections among the chips and printed circuit board (PCB). To better…”
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Hardware ODE solvers using stochastic circuits by Siting Liu, Jie Han

“…A novel ordinary differential equation (ODE) solver is proposed by using a stochastic integrator to implement the accumulative function of the Euler method. We…”
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TritonRoute: An Initial Detailed Router for Advanced VLSI Technologies by Kahng, Andrew B., Wang, Lutong, Xu, Bangqi

“…Detailed routing is a dead-or-alive critical element in design automation tooling for advanced node enablement. However, very few works address detailed…”
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Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems by Chen, Ming-Hung, Chang, Yao-Wen, Wang, Jun-Jie

“… To optimize the performance of such a system, we shall develop a simultaneous partitioning and routing algorithm considering the timing penalty…”
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Lamellar DSA-aware Detailed Routing Considering Double Patterning and Short Template Minimization by Wu, Kuei-Lin, Fang, Shao-Yun

“…With the advance of technology nodes, via fabrication in a dense design becomes a difficult challenge, and the directed self-assembly (DSA) technology has…”
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Skew-Oblivious Data Routing for Data Intensive Applications on FPGAs with HLS by Chen, Xinyu, Tan, Hongshi, Chen, Yao, He, Bingsheng, Wong, Weng-Fai, Chen, Deming

“…FPGAs have become emerging computing infrastructures for accelerating applications in datacenters. Meanwhile, high-level synthesis (HLS) tools have been…”
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SMT-Based Cost Optimization Approach for the Integration of Avionic Functions in IMA and TTEthernet Architectures by Beji, Sofiene, Hamadou, Sardaouna, Gherbi, Abdelouahed, Mullins, John

“…The design of avionic systems is a complex engineering activity. The iterative integration approach helps in controlling the complexity of such activity. On…”
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Cache-Conscious Wavefront Scheduling by Rogers, Timothy G., O'Connor, Mike, Aamodt, Tor M.

“…This paper studies the effects of hardware thread scheduling on cache management in GPUs. We propose Cache-Conscious Wave front Scheduling (CCWS), an adaptive…”
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