Search Results - Low-Power VLSI Circuit Design and Optimization

Design Optimization of Low power VLSI Circuits in Deep Submicron Technology by Chaitanya, U, Sankar, K Jaya, Murthy, M V Ramana, Naraiah, R, Ahammed, M D Javeed, Balaji, B

“…[...]it is vital to look at new device structural model to promote the growth of the VLSI design industry in nano-scale production…”
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Design methodologies and circuit optimization techniques for low power CMOS VLSI design by Geetha, B. T., Padmavathi, B., Perumal, V.

“…Low power is the real test for late hardware businesses. Control scattering is an essential thought as far as execution and area for VLSI Chip outline…”
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Design and Optimization of Low-Power VLSI Circuits for IoT Devices by Saxena, Aditi, Haripriya, D., Madan, Parul, Srivastava, Arun Pratap, Shalini, N, Kumar, Anil

“… This study explores the "Design and Optimization of Low-Power VLSI Circuits for IoT Devices," with an eye on striking a good power-to-performance ratio…”
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Design and optimization of power management circuits for low-power VLSI systems by Ramashri, T., Christy, A. Ananthi, Abdul Munaf, K, Gowri, V., Ramesh, D. Raja, Deivakani, M.

“…This study delves into the topic of low-power VLSI system power management circuit design and optimization…”
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Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms by Mahnoor Maghroori, Mehdi Dolatshahi

“…This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits…”
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EXPLORING NOVEL DESIGN APPROACH FOR LOW POWER VLSI IN IOT DEVICES by B, Anuradha, M.S., Kavitha, S, Karthik, N, Karthikeyan

“…Circuit-level optimization is a critical aspect of designing low-power VLSI circuits for IoT devices…”
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Designing of ultra‐low‐power high‐speed repeaters for performance optimization of VLSI interconnects at 32 nm by Khursheed, Afreen, Khare, Kavita, Haque, Fozia Zia

“…This paper resolves the performance issue encountered in very‐large‐scale integration interconnects due to downsizing of integrated circuits…”
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Interconnect Technology/System Co-Optimization for Low-Power VLSI Applications Using Ballistic Materials by Pei, Zhenlin, Dutta, Arin, Shang, Liuting, Jung, Sungyong, Pan, Chenyun

“…), and contact resistance. Furthermore, to achieve maximal chip-level throughput, two interconnect design schemes are proposed and optimized under a given number of metal layers, die area, and power density constraints…”
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VLSI Synthesis for Low-Power Clocking in Synchronous Designs by Hussein, Naseer Alwan, Hameed, Maan, Khamees, Luay Ali

“…In the field of information theory, the significance of low-power techniques cannot be overstated…”
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A Novel Low-Power N-bit Comparator Design with Optimized Transistor Count for Energy-Efficient VLSI Applications by Chouhan, Jitendra, Singh, Abhay Pratap, Baghel, R. K.

“…In this research, a novel low-power N-bit digital comparator is proposed, demonstrating significant improvements in transistor count, power dissipation, and speed compared to existing designs…”
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Hybrid quantum-classical framework for optimizing low-power VLSI circuits in IoTdevices by Manan Mujahid, Md, Jose, Deepa

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A delay-constrained optimization framework for low-power VLSI interconnect design using mathematical signal models by Rajkumar, V., Amutha, R.

“…As VLSI technology scales to sub-7 nm nodes, interconnect-related delay and power dissipation become dominant design bottlenecks…”
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Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization by Thangam, C., Manjith, R.

“…A novel approach to achieve low power consumption during Built-In Self-Test (BIST) operations in Very Large Scale Integrated…”
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Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications by Singh, Balraj, Gola, Deepti, Goel, Ekta, Kumar, Sanjay, Singh, Kunal, Jit, Satyabrata

“… Since only little work has been carried out on the performance optimization of the JLFETs, the present work is believed to be very useful for designing the low-power VLSI circuits using DP-DG JLFETs…”
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An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree by Chang, Shang-Yuan, Wu, Bing-Chen, Liou, Yi-Long, Zheng, Rui-Xuan, Lee, Pei-Lin, Chiueh, Tzi-Dar, Liu, Tsung-Te

“… The ultra-low-power feature is achieved by an algorithm-hardware co-design approach that jointly considers optimization opportunities across the algorithm, architecture, and circuit levels to minimize power consumption…”
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Exploring analog VLSI architectures for linear regulators and high-speed receivers: a comprehensive SLR and emerging innovations by Nagula, Suresh, Patri, Sreehari Rao, Goel, Ekta

“…This paper thoroughly examines the current research on analog VLSI designs, with an emphasis on linear regulators and high-speed receivers…”
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Adiabatic logic based circuit optimization for ultra low power applications by Sharma, Manoj

“…In this paper authors have presented a design and experimentation evaluation of circuit optimization inspired by adiabatic logic processing…”
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Design and Implementation of Low Power, Area Crosstalk Reduction Using Static Timing Analysis by Obulesu, Battari, Ashok, P., Rajesh, J., Madhu, K., Rakesh, G., Raghava Sarath Chandra Reddy, Guddety

“… This procedure reduces the crosstalk issue by using the improved logic architecture. The proposed approach utilizes a combination of circuit-level optimization techniques…”
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Innovative Techniques in the Construction of Very Large Scale Integration Circuits for Low-Power and High-Performance Circuits by Saravanan, V., Sasikala, G., Gomathi, P., Kirubakaran, D., Rajalingam, A., Pagunuran, Jubert R.

“… This research investigates low-power, high-performance VLSI circuit construction methods. We start with VLSI design fundamentals and power management and performance optimization concerns…”
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ONOFIC approach: low power high speed nanoscale VLSI circuits design by Sharma, V.K., Pattanaik, M., Raj, B.

“… Minimising the chip area is not a lonely optimisation performance factor for a VLSI chip designer…”
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