Výsledky vyhledávání - IEEE International Conference on Algorithms AND Architectures for Parallel Processing~

ICAPP 95 : IEEE First ICA[3]PP : IEEE First International Conference on Algorithms and Architectures for Parallel Processing, Brisbane, Australia, 19-21 April, 1995 Autor IEEE International Conference on Algorithms and Architectures for Parallel Processing, Narasimhan, V. L.

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Proceedings fifth International Conference on algorithms and architectures for parallel processing Autor IEEE International Conference on Algorithms and Architectures for Parallel Processing, Zhou, Wanlei

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Proceedings of 1996 IEEE Second International Conference on Algorithms & Architectures for Parallel Processing, ICA[3]PP '96, June 11-13, 1996, Singapore Autor IEEE International Conference on Algorithms and Architectures for Parallel Processing, Institute of Electrical and Electronics Engineers. Singapore Section, IEEE Singapore Section. Computer Chapter, National University of Singapore. Dept. of Information Systems and Computer Science

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1997 3rd International Conference on Algorithms & Architectures for Parallel Processing, ICA[3]PP '97, Melbourne, Australia Decsmber 10-12 1997 Autor IEEE International Conference on Algorithms and Architectures for Parallel Processing, Institute of Electrical and Electronics Engineers. Victorian section, Gościński, Andrzej, Hobbs, Michael, Zhou, Wanlei, Deakin University Faculty of Science and Technology, Deakin University IEEE Victorian Section

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Algorithms and architectures for parallel processing: 1997 3rd international conference, Melbourne, Australia, December 10-12 1997 Autor Goscinski, Andrzej, Zhou, Wanlei, Hobbs, Michael

“…This volume of proceedings describes the lower costs and higher degrees of integration of chip architecture which allow parallel processing…”
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Neural Speech Phase Prediction Based on Parallel Estimation Architecture and Anti-Wrapping Losses Autor Ai, Yang, Ling, Zhen-Hua

“… The proposed model is a cascade of a residual convolutional network and a parallel estimation architecture…”
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InnerSP: A Memory Efficient Sparse Matrix Multiplication Accelerator with Locality-Aware Inner Product Processing Autor Baek, Daehyeon, Hwang, Soojin, Heo, Taekyung, Kim, Daehoon, Huh, Jaehyuk

“… To mitigate the memory access overheads, recent accelerator designs advocated the outer product processing which minimizes input accesses but generates intermediate products to be merged to the final output matrix…”
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Skywalker: Efficient Alias-Method-Based Graph Sampling and Random Walk on GPUs Autor Wang, Pengyu, Li, Chao, Wang, Jing, Wang, Taolei, Zhang, Lu, Leng, Jingwen, Chen, Quan, Guo, Minyi

“…Graph sampling and random walk operations, capturing the structural properties of graphs, are playing an important role today as we cannot directly adopt computing-intensive algorithms on large-scale graphs…”
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Splitwise: Efficient Generative LLM Inference Using Phase Splitting Autor Patel, Pratyush, Choukse, Esha, Zhang, Chaojie, Shah, Aashaka, Goiri, Inigo, Maleki, Saeed, Bianchini, Ricardo

“…Generative large language model (LLM) applications are growing rapidly, leading to large-scale deployments of expensive and power-hungry GPUs. Our…”
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Accelerating Graph Convolutional Networks Using Crossbar-based Processing-In-Memory Architectures Autor Huang, Yu, Zheng, Long, Yao, Pengcheng, Wang, Qinggang, Liao, Xiaofei, Jin, Hai, Xue, Jingling

“… efficiency.In this paper, we present a new GCN accelerator, RE-FLIP, with three key innovations in terms of architecture design, algorithm mappings, and practical implementations…”
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A Hybrid Systolic-Dataflow Architecture for Inductive Matrix Algorithms Autor Weng, Jian, Liu, Sihao, Wang, Zhengrong, Dadu, Vidushi, Nowatzki, Tony

“… in the hardware/software interface, then a spatial architecture could efficiently execute parallel code regions…”
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pSyncPIM: Partially Synchronous Execution of Sparse Matrix Operations for All-Bank PIM Architectures Autor Baek, Daehyeon, Hwang, Soojin, Huh, Jaehyuk

“… Sparse matrix processing is another critical computation that can significantly benefit from the PIM architecture, but the current all-bank PIM control cannot support diverging executions due to the random sparsity…”
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MAD-Max Beyond Single-Node: Enabling Large Machine Learning Model Acceleration on Distributed Systems Autor Hsia, Samuel, Golden, Alicia, Acun, Bilge, Ardalani, Newsha, DeVito, Zachary, Wei, Gu-Yeon, Brooks, David, Wu, Carole-Jean

“…Training and deploying large-scale machine learning models is time-consuming, requires significant distributed computing infrastructures, and incurs high…”
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Parallelizing Maximal Clique Enumeration on GPUs Autor Almasri, Mohammad, Chang, Yen-Hsiang, Hajj, Izzat El, Nagi, Rakesh, Xiong, Jinjun, Hwu, Wen-mei

“…We present a GPU solution for exact maximal clique enumeration (MCE) that performs a search tree traversal following the Bron-Kerbosch algorithm…”
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PolyGraph: Exposing the Value of Flexibility for Graph Processing Accelerators Autor Dadu, Vidushi, Liu, Sihao, Nowatzki, Tony

“… First, we identify a taxonomy of key algorithm variants. Then we develop a template architecture (PolyGraph…”
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MnnFast: A Fast and Scalable System Architecture for Memory-Augmented Neural Networks Autor Jang, Hanhwi, Kim, Joonsung, Jo, Jae-Eon, Lee, Jaewon, Kim, Jangwoo

“… Such large-scale memory networks provide excellent reasoning power; however, the current computer infrastructure cannot achieve scalable performance due to its limited system architecture…”
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An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives Autor Klenk, Benjamin, Jiang, Nan, Thorson, Greg, Dennison, Larry

“…The slowdown of single-chip performance scaling combined with the growing demands of computing ever larger problems efficiently has led to a renewed interest in distributed architectures and specialized hardware…”
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DRRA-based Reconfigurable Architecture for Mixed-Radix FFT Autor Kallapu, Reeshita, Stathis, Dimitrios, Boppu, Srinivas, Hemani, Ahmed

“… In this paper, we propose an architecture for the implementation of the FFT that is derived from the Dynamically Reconfigurable Resource Array and has multiple parallel processing cells while also…”
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Seer: Predictive Runtime Kernel Selection for Irregular Problems Autor Swann, Ryan, Osama, Muhammad, Sangaiah, Karthik, Mahmud, Jalal

“…Modern GPUs are designed for regular problems and suffer from load imbalance when processing irregular data…”
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Accelerating Fourier and Number Theoretic Transforms using Tensor Cores and Warp Shuffles Autor Durrani, Sultan, Chughtai, Muhammad Saad, Hidayetoglu, Mert, Tahir, Rashid, Dakkak, Abdul, Rauchwerger, Lawrence, Zaffar, Fareed, Hwu, Wen-mei

“… To speed things up, fast Fourier transform (FFT) algorithms, which are reduced-complexity formulations for computing the DFT of a sequence, have been proposed and implemented for traditional processors and their corresponding instruction sets…”
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