Search Results - Hardware Integrated circuits Semiconductor memory Static memory

Perceptron-Based Prefetch Filtering by Bhatia, Eshan, Chacon, Gino, Pugsley, Seth, Teran, Elvira, Gratz, Paul V., Jimenez, Daniel A.

“…Hardware prefetching is an effective technique for hiding cache miss latencies in modern processor designs…”
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CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability by Hassan, Hasan, Patel, Minesh, Kim, Jeremie S., Yaglikci, A. Giray, Vijaykumar, Nandita, Ghiasi, Nika Mansouri, Ghose, Saugata, Mutlu, Onur

“…DRAM has been the dominant technology for architecting main memory for decades. Recent trends in multi-core system design and large-dataset applications have amplified the role of DRAM as a critical system bottleneck…”
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The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions by Patel, Minesh, Kim, Jeremie S., Mutlu, Onur

“…Modern DRAM-based systems suffer from significant energy and latency penalties due to conservative DRAM refresh standards. Volatile DRAM cells can retain…”
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Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design by Qureshi, Moinuddin K., Loh, Gabe H.

“…This paper analyzes the design trade-offs in architecting large-scale DRAM caches. Prior research, including the recent work from Loh and Hill, have organized…”
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Late Breaking Results: Versatile 4:1 Multiplexer Using 1T1R RRAM Crossbar for High Speed In-Memory Computing by Vinodh Kumar, B, Kailath, Binsu J

“…This paper presents a high speed NAND based 4:1 Multiplexer (MUX) for various logic operations in a ResistiveRandom access memory crossbar structure…”
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333-eDRAM - 3T Embedded DRAM Leveraging Monolithic 3D Integration of 3 Transistor Types: IGZO, Carbon Nanotube and Silicon FETs by Kong, David, Prakash, Shvetank, Kufel, Jedrzej, Kyriazidis, Georgios, Omri, Yasmine, Verity, David, Ozer, Emre, Reddi, Vijay Janapa, Hills, Gage

“… We present an energy- and area-efficient embedded DRAM memory architecture (quantified by EADP: the product of total energy consumption, circuit area footprint and application execution time…”
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MORSE: Memory Overwrite Time Guided Soft - Writes to Improve ReRAM Energy and Endurance by Singh, Devesh, Yeung, Donald

“…ReRAM is an attractive main memory technology due to its high density and low idle power…”
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HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging by Marazzi, Michele, Sachsenweger, Tristan, Solt, Flavien, Zeng, Peng, Takashi, Kubo, Yarema, Maksym, Razavi, Kaveh

“… Unfortunately, this hinders academic research that focuses on studying or improving DRAM. Without knowing the circuit topology, transistor dimensions, and layout…”
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DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands by Nam, Hwayong, Baek, Seungmin, Wi, Minbok, Kim, Michael Jaemin, Park, Jaehyun, Song, Chihun, Kim, Nam Sung, Ahn, Jung Ho

“…The demand for precise information on DRAM microarchitectures and error characteristics has surged, driven by the need to explore processing in memory, enhance reliability, and mitigate security vulnerability…”
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Native DRAM Cache: Re-architecting DRAM as a Large-Scale Cache for Data Centers by Ryu, Yesin, Kim, Yoojin, Jung, Giyong, Ahn, Jung Ho, Kim, Jungrae

“… These innovations facilitate Caching-In-Memory (CIM) and enable NDC to serve as a high-capacity LLC with high set-associativity, low-latency, high-throughput, and low-energy…”
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Triangel: A High-Performance, Accurate, Timely On-Chip Temporal Prefetcher by Ainsworth, Sam, Mukhanov, Lev

“…Temporal prefetching, where correlated pairs of addresses are logged and replayed on repeat accesses, has recently become viable in commercial designs. Arm's…”
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PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs by Shubham, Sai, Pandit, Shubham, Prasad, Kailash, Mekie, Joycee

“…This work introduces PVC-RAM, a process variation aware in-memory computing (IMC) static random-access memory…”
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Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories by Waqar, Faaiq, Zhang, Jiahao, Lu, Anni, He, Zifan, Cong, Jason, Yu, Shimeng

“…) transistors to implement configuration memory and pass gates, significantly improving area, latency, and power efficiency…”
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Asymmetric Predictive Testing for Aging in SRAMs by Lin, Yunkun, Li, Mingye, Gupta, Sandeep

“…To avoid corruption of user data, predictive testing methods have been proposed to identify SRAMs likely to fail in the near future due to aging. These methods…”
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Low-Cost 7T-SRAM Compute-In-Memory Design based on Bit-Line Charge-Sharing based Analog-To-Digital Conversion by Lee, Kyeongho, Kim, Joonhyung, Park, Jongsun

“…Although compute-in-memory (CIM) is considered as one of the promising solutions to overcome memory wall problem, the variations in analog voltage computation and analog-to-digital-converter (ADC…”
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A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration by Lee, Kyeongho, Cheon, Sungsoo, Jo, Joongho, Choi, Woong, Park, Jongsun

“…) to reduce the hardware cost of an analog readout circuit while supporting higher precision MAC operations…”
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AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling by Zhang, Qijun, Lu, Yao, Li, Mengming, Xie, Zhiyao

“…Power efficiency is a critical design objective in modern CPU design. Architects need a fast yet accurate architecture-level power evaluation tool to perform…”
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Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs by Liu, Liu, Kumar, Shubham, Thomann, Simon, Amrouch, Hussam, Hu, Xiaobo Sharon

“…Ternary content addressable memory (TCAM), widely used in network routers and high-associativity caches, is gaining popularity in machine learning and data-analytic applications…”
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Die Stacking (3D) Microarchitecture by Black, Bryan, Annavaram, Murali, Brekelbaum, Ned, DeVale, John, Jiang, Lei, Loh, Gabriel H., McCaule, Don, Morrow, Pat, Nelson, Donald W., Pantuso, Daniel, Reed, Paul, Rupley, Jeff, Shankar, Sadasivan, Shen, John, Webb, Clair

“…3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface…”
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PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table by Jeon, JaeHwa, Hong, Jae-Youn, Kim, Sunghoon, Choi, Insu, Yang, Joon-Sung

“…This paper proposes a novel memory architecture, PIE-DRAM, to mitigate the performance overhead caused by IECC…”
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