Výsledky vyhledávání - Hardware Integrated circuits Logic circuits Sequential circuits
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Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking
Vydáno: IEEE 22.06.2025Vydáno v 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…Combinational Equivalence Checking (CEC) is a crucial technique in electronic design automation for verifying the functional equivalence of combinational circuits…”
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PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT
Vydáno: IEEE 22.06.2025Vydáno v 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“… However, as the size and complexity of circuits grow, SAT-based ATPG faces challenges like pattern inflation and excessive runtime, limiting its overall performance…”
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qSeq: Full Algorithmic and Tool Support for Synthesizing Sequential Circuits in Superconducting SFQ Technology
Vydáno: IEEE 05.12.2021Vydáno v 2021 58th ACM/IEEE Design Automation Conference (DAC) (05.12.2021)“…Synthesizing general nonlinear sequential circuits in superconducting Single Flux Quantum (SFQ…”
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Synthesis of statically analyzable accelerator networks from sequential programs
ISSN: 1558-2434Vydáno: ACM 01.11.2016Vydáno v Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design (01.11.2016)“…This paper describes a general framework for transforming a sequential program into a network of processes, which are then converted to hardware accelerators through high level synthesis…”
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Optimal circuits for parallel bit reversal
Vydáno: IEEE 01.06.2017Vydáno v 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) (01.06.2017)“…In this paper, we develop novel parallel circuit designs for calculating the bit reversal…”
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SeGen: Automatic Topology Generator for Sequencing Elements
ISSN: 1558-2434Vydáno: ACM 27.10.2024Vydáno v Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design (27.10.2024)“…Sequencing elements, such as flip-flops (FFs), significantly impact the speed, size, and power consumption of digital integrated circuits…”
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Minimizing area and power of sequential CMOS circuits using threshold decomposition
ISBN: 9781450315739, 1450315739ISSN: 1092-3152Vydáno: New York, NY, USA ACM 05.11.2012Vydáno v 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (05.11.2012)“…This paper describes the design of a standard cell library of differential mode threshold gates, referred to as a Threshold Logic Latch or TLL, and new threshold function identification…”
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Security against hardware Trojan through a novel application of design obfuscation
ISSN: 1092-3152Vydáno: IEEE 02.11.2009Vydáno v 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers (02.11.2009)“…Malicious hardware Trojan circuitry inserted in safety-critical applications is a major threat to national security…”
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Dynamic Verification of Sequential Consistency
ISBN: 076952270X, 9780769522708ISSN: 1063-6897Vydáno: Washington, DC, USA IEEE Computer Society 01.05.2005Vydáno v 32nd International Symposium on Computer Architecture (ISCA'05) (01.05.2005)“… One such consistency model is sequential consistency (SC), which specifies that all loads and stores appear to execute in a total order that respects program order for each thread…”
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Power gating applied to MP-SoCs for standby-mode power management
ISBN: 1450320716, 9781450320719ISSN: 0738-100XVydáno: New York, NY, USA ACM 29.05.2013Vydáno v 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) (29.05.2013)“…Complex SoCs from servers to intelligent sensors are increasingly built up from heterogeneous IP cores and subsystems. Accelerator blocks or additional…”
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Polynomial arithmetic using sequential stochastic logic
Vydáno: ACM 18.05.2016Vydáno v Proceedings of the 26th Edition on Great Lakes Symposium on VLSI (18.05.2016)“…We present the design of stochastic computing systems based on sequential logic to implement arbitrary polynomial functions…”
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Efficient generation of counterexamples and witnesses in symbolic model checking
ISBN: 0897917251, 9780897917254Vydáno: New York, NY, USA ACM 01.01.1995Vydáno v Proceedings of the 32nd annual ACM/IEEE Design Automation Conference (01.01.1995)Získat plný text
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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients
ISBN: 1581134614, 9781581134612ISSN: 0738-100XVydáno: New York, NY, USA ACM 10.06.2002Vydáno v Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002 (10.06.2002)“…In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge, therefore they generate substrate noise due to the sharp peaks on the supply current…”
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Skewed flip-flop transformation for minimizing leakage in sequential circuits
ISBN: 1595936270, 9781595936271ISSN: 0738-100XVydáno: New York, NY, USA ACM 04.06.2007Vydáno v 2007 44th ACM/IEEE Design Automation Conference (04.06.2007)“… However, current approaches target the combinational circuits even though sequential elements, such as flip-flops, contribute an appreciable proportion of the total leakage…”
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EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components
Vydáno: IEEE 22.06.2025Vydáno v 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“… However, for large-scale industrial sequential circuits, these simulations are time-consuming, creating a significant bottleneck in chip development…”
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Equivalence Checking of Sequential Quantum Circuits
ISSN: 0278-0070, 1937-4151Vydáno: New York IEEE 01.09.2022Vydáno v IEEE transactions on computer-aided design of integrated circuits and systems (01.09.2022)“…We define a formal framework for equivalence checking of sequential quantum circuits…”
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Conflict driven learning in a quantified Boolean Satisfiability solver
ISBN: 0780376072, 9780780376076ISSN: 1092-3152Vydáno: New York, NY, USA ACM 10.11.2002Vydáno v Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design (10.11.2002)“…) as many interesting sequential circuit verification problems can be formulated as QBF instances…”
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Sequential Circuits Synthesis for Rapid Single Flux Quantum Logic Based on Finite State Machine Decomposition
ISSN: 0278-0070, 1937-4151Vydáno: New York IEEE 01.10.2023Vydáno v IEEE transactions on computer-aided design of integrated circuits and systems (01.10.2023)“… Logic synthesis is crucial in converting behavioral circuit description into a circuit netlist, typically combining combinational and sequential circuit synthesis…”
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Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG
ISBN: 0769518702, 9780769518701ISSN: 1530-1591Vydáno: Washington, DC, USA IEEE Computer Society 03.03.2003Vydáno v Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003 (03.03.2003)Získat plný text
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Automatic functional test generation using the extended finite state machine model
ISBN: 9780897915779, 0897915771Vydáno: New York, NY, USA ACM 01.01.1993Vydáno v DAC 93: 30th ACM-IEEE Design Automation (01.01.1993)Získat plný text
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