Search Results - Hardware Integrated circuits Logic circuits Design modules and hierarchy

Using module-level Evolvable Hardware approach in design of sequential logic circuits by Yanyun Tao, Jian Cao, Yuzhen Zhang, Jiajun Lin, Minglu Li

“…In this study, we propose a module-level Evolvable Hardware (EHW) approach to design synchronous sequential circuits and minimize the circuit complexity…”
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Neuron MOS Binary-Logic Integrated Circuits - Part I: Design Fundamentals and Soft- Hardware-Logic Circuit Implementation by 大見 忠弘

“… One of the most striking features of vMOS binary-logic application is the realization of a so-called Soft Hardware Logic Circuit…”
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Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation by Shibata, T., Ohmi, T.

“…Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor ( nu MOS…”
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Early estimation of aging in the design flow of integrated circuits through a programmable hardware module by Sandionigi, Chiara, Altieri, Mauricio, Heron, Olivier

“…Integrated circuits' aging is recognized as a key reliability bottleneck and its estimation at design time becomes mandatory to guarantee performance and lifetime of the circuit…”
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Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems : Design of circuits and integrated systems by SILVA, M. L, FERREIRA, J. C

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System for Collaborative Hardware RTL Logic Timing Debug in Integrated Circuit Designs

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US Patent Issued to International Business Machines on March 25 for "System for collaborative hardware RTL logic timing debug in integrated circuit designs" (American, Indian Inventors)

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Tartan: Microarchitecting a Robotic Processor by Bakhshalipour, Mohammad, Gibbons, Phillip B.

“…This paper presents Tartan, a CPU architecture designed for a wide range of robotic applications. Tartan provides architectural support for common robotic…”
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The design and use of simplepower: a cycle-accurate energy estimation tool by Ye, W., Vijaykrishnan, N., Kandemir, M., Irwin, M. J.

“…In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for ev aluating the effect of high-level algorithmic, architectural, and compilation trade-offs on energy…”
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Lower power by voltage stacking: A fine-grained system design approach by Blutman, Kristof, Kapoor, Ajay, Martinez, Jacinto Garcia, Fatemi, Hamed, de Gyvez, Jose Pineda

“…Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery…”
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VEAL: Virtualized Execution Accelerator for Loops by Clark, Nathan, Hormati, Amir, Mahlke, Scott

“…Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific…”
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Influence of compiler optimizations on system power by Kandemir, M., Vijaykrishnan, N., Irwin, M. J., Ye, W.

“…High-level compiler optimizations ha ve been widely used to ac hiev e speedups on array-based codes. Su ch optimizations are becoming increasingly important in…”
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FSMM: An Efficient Matrix Multiplication Accelerator Supporting Flexible Sparsity by Qiao, Yuxuan, Yang, Fan, Zhang, Yecheng, Xiong, Xiankui, Yao, Xiao, Yao, Haidong

“… Traditional accelerators, equipped with additional hardware units to address this issue, often experience the issue of low hardware utilization. Furthermore, N…”
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An O(m+n)-Space Spatiotemporal Denoising Filter with Cache-Like Memories for Dynamic Vision Sensors by Zhao, Qinghang, Wang, Jiaqi, Ji, Yixi, Wu, Jinjian, Shi, Guangming

“… Spatiotemporal filter is an effective and hardware-friendly solution for DVS denoising but previous designs have large memory overhead or degraded performance issues…”
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Achieving Out-of-Order Performance with Almost In-Order Complexity by Tseng, Francis, Patt, Yale N.

“… However, traditional methods of increasing issue width do not scale; that is, they drastically increase design complexity and power requirements…”
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Enforcing architectural contracts in high-level synthesis by Patil, Nikhil, Bansal, Ankit, Chiou, Derek

“… We describe a prototype compiler that generates control required to enforce the contract, and thus, synthesizes the pair of descriptions to hardware…”
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Operating system based software generation for systems-on-chip by Desmet, Dirk, Verkest, D., De Man, Hugo

“…) designs, including real-time embedded software. While many SOC modeling languages originate from hardware description languages, and thus tend to describe statical architectures, we observe that embedded software makes SOC designs essentially…”
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Memory aware compilation through accurate timing extraction by Grun, Peter, Dutt, Nikil, Nicolau, Alex

“…Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode…”
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An N-Way Group Association Architecture and Sparse Data Group Association Load Balancing Algorithm for Sparse CNN Accelerators by Wang, Jingyu, Yuan, Zhe, Liu, Ruoyang, Yang, Huazhong, Liu, Yongpan

“…) a Sparse Data Group Association Load Balancing Algorithm which is implemented by the Scheduler module in the architecture to reduce the collision rate and improve the performance…”
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Bus encoding for low-power high-performance memory systems by Chang, Naehyuck, Kim, Kwanho, Cho, Jinsung

“…), Gunning Transfer Logic (GTL+) and Stub Series Termination Logic (SSTL_2) which are widely used…”
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