Výsledky vyhledávání - Hardware Integrated circuits Logic circuits Design modules AND hierarchy

Tartan: Microarchitecting a Robotic Processor Autor Bakhshalipour, Mohammad, Gibbons, Phillip B.

“…This paper presents Tartan, a CPU architecture designed for a wide range of robotic applications. Tartan provides architectural support for common robotic…”
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The design and use of simplepower: a cycle-accurate energy estimation tool Autor Ye, W., Vijaykrishnan, N., Kandemir, M., Irwin, M. J.

“…In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for ev aluating the effect of high-level algorithmic, architectural, and compilation trade-offs on energy…”
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VEAL: Virtualized Execution Accelerator for Loops Autor Clark, Nathan, Hormati, Amir, Mahlke, Scott

“…Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific…”
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Lower power by voltage stacking: A fine-grained system design approach Autor Blutman, Kristof, Kapoor, Ajay, Martinez, Jacinto Garcia, Fatemi, Hamed, de Gyvez, Jose Pineda

“…Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery…”
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Influence of compiler optimizations on system power Autor Kandemir, M., Vijaykrishnan, N., Irwin, M. J., Ye, W.

“…High-level compiler optimizations ha ve been widely used to ac hiev e speedups on array-based codes. Su ch optimizations are becoming increasingly important in…”
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FSMM: An Efficient Matrix Multiplication Accelerator Supporting Flexible Sparsity Autor Qiao, Yuxuan, Yang, Fan, Zhang, Yecheng, Xiong, Xiankui, Yao, Xiao, Yao, Haidong

“… Traditional accelerators, equipped with additional hardware units to address this issue, often experience the issue of low hardware utilization. Furthermore, N…”
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Achieving Out-of-Order Performance with Almost In-Order Complexity Autor Tseng, Francis, Patt, Yale N.

“… However, traditional methods of increasing issue width do not scale; that is, they drastically increase design complexity and power requirements…”
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An O(m+n)-Space Spatiotemporal Denoising Filter with Cache-Like Memories for Dynamic Vision Sensors Autor Zhao, Qinghang, Wang, Jiaqi, Ji, Yixi, Wu, Jinjian, Shi, Guangming

“… Spatiotemporal filter is an effective and hardware-friendly solution for DVS denoising but previous designs have large memory overhead or degraded performance issues…”
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Enforcing architectural contracts in high-level synthesis Autor Patil, Nikhil, Bansal, Ankit, Chiou, Derek

“… We describe a prototype compiler that generates control required to enforce the contract, and thus, synthesizes the pair of descriptions to hardware…”
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Operating system based software generation for systems-on-chip Autor Desmet, Dirk, Verkest, D., De Man, Hugo

“…) designs, including real-time embedded software. While many SOC modeling languages originate from hardware description languages, and thus tend to describe statical architectures, we observe that embedded software makes SOC designs essentially…”
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Memory aware compilation through accurate timing extraction Autor Grun, Peter, Dutt, Nikil, Nicolau, Alex

“…Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode…”
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Bus encoding for low-power high-performance memory systems Autor Chang, Naehyuck, Kim, Kwanho, Cho, Jinsung

“…), Gunning Transfer Logic (GTL+) and Stub Series Termination Logic (SSTL_2) which are widely used…”
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Evaluation of a high performance code compression method Autor Lefurgy, Charles, Piccininni, Eva, Mudge, Trevor

“… In this paper, we investigate the performance penalty of a hardware-managed code compression algorithm recently introduced in IBM's PowerPC 405…”
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An N-Way Group Association Architecture and Sparse Data Group Association Load Balancing Algorithm for Sparse CNN Accelerators Autor Wang, Jingyu, Yuan, Zhe, Liu, Ruoyang, Yang, Huazhong, Liu, Yongpan

“…) a Sparse Data Group Association Load Balancing Algorithm which is implemented by the Scheduler module in the architecture to reduce the collision rate and improve the performance…”
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Address code generation for digital signal processors Autor Udayanarayanan, Sathishkumar, Chakrabarti, Chaitali

“…In this paper we propose a procedure to generate code with minimum number of addressing instructions. We analyze different methods of generating addressing…”
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Compiling Esterel into sequential code Autor Edwards, Stephen A.

“…Embedded real-time software systems often need fine-grained parallelism and precise control over time, things typical real-time operating systems do not…”
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Microcoded Architectures for Ion-Tap Quantum Computers Autor Kreger-Stickles, Lucas, Oskin, Mark

“…In this paper we present the first ever systematic design space exploration of microcoded software fault tolerant ion-trap quantum computers…”
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Utilizing memory bandwidth in DSP embedded processors Autor Gebotys, Catherine H.

“…This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently…”
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Low-cost branch folding for embedded applications with small tight loops Autor Lee, Lea Hwang, Scott, Jeff, Moyer, Bill, Arends, John

“… In this paper, we propose a hardware technique for folding out branches when executing these small loops…”
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Predicting performance potential of modern DSPs Autor Ghazal, Naji, Newton, Richard, Rabaey, Jan

“…High-level development tools for digital signal processors (DSPs) remain unable to extract optimal performance from them without the designer's in-depth…”
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