Výsledky vyhledávání - Hardware Integrated circuits Logic circuits Arithmetic and datapath circuits

Bit-pragmatic deep neural network computing Autor Albericio, Jorge, Delmás, Alberto, Judd, Patrick, Sharify, Sayeh, O'Leary, Gerard, Genov, Roman, Moshovos, Andreas

“…Deep Neural Networks expose a high degree of parallelism, making them amenable to highly data parallel architectures. However, data-parallel architectures…”
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A new stochastic computing multiplier with application to deep convolutional neural networks Autor Hyeonuk Sim, Jongeun Lee

“…Stochastic computing (SC) allows for extremely low cost and low power implementations of common arithmetic operations…”
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Architectural-space exploration of approximate multipliers Autor Rehman, Semeen, El-Harouni, Walaa, Shafique, Muhammad, Kumar, Akash, Henkel, Jorg

“…This paper presents an architectural-space exploration methodology for designing approximate multipliers. Unlike state-of-the-art, our methodology generates…”
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A low latency generic accuracy configurable adder Autor Shafique, Muhammad, Ahmad, Waqas, Hafiz, Rehan, Henkel, Jorg

“… An error correction unit is integrated to provide accurate results for cases where high accuracy is required…”
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Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks Autor Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee, Kiyoung Choi

“… The approach allows an easy implementation of early decision termination with a fixed hardware design by exploiting the progressive precision characteristics of stochastic computing, which was not…”
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Stochastic circuits for real-time image-processing applications Autor Alaghi, Armin, Li, Cheng, Hayes, John P.

“… We show how stochastic circuits can be integrated at the pixel level with image sensors, thus supporting efficient real-time (pre…”
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Equivalence among stochastic logic circuits and its application Autor Te-Hsuan Chen, Hayes, John P.

“… It implements arithmetic operations by extremely simple and low-power hardware. Despite major new applications, SC's theory and design requirements are poorly understood…”
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Measurement-based uncomputation of quantum circuits for modular arithmetic Autor Luongo, Alessandro, Miti, Antonio Michele, Narasimhachar, Varun, Sireesh, Adithya

“…% for modular adders based on the architecture of [2]. Our results have the potential to improve other circuits for modular arithmetic, such as modular multiplication…”
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Logic Synthesis for Digital In-Memory Computing Autor Haq Rashed, Muhammad Rashedul, Kumar Jha, Sumit, Ewetz, Rickard

“… State-of-the-art digital in-memory computing schemes rely on manually decomposing arithmetic operations into in-memory compute kernels…”
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An Enhanced Data Packing Method for General Matrix Multiplication in Brakerski/Fan-Vercauteren Scheme Autor Meng, Xiangchen, Tan, Yan, Jiang, Zijun, Lyu, Yangdi

“… Furthermore, we design specialized hardware…”
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Precon: A Precision-Convertible Architecture for Accelerating Quantized Deep Learning Models across Various Domains Including LLMs Autor Park, Jongwoo, Kim, Hyeonseong, Han, Jiyun, Choi, Seungkyu

“… By enabling on-the-fly switching between half-float (FP16) decoding and integer (INT) decomposition, the design effectively supports INT4-FP16, INT4-INT4, and INT4INT8 arithmetic within shared logic…”
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PolyCleaner: Clean your Polynomials before Backward Rewriting to verify Million-gate Multipliers Autor Mahzoon, Alireza, Grosse, Daniel, Drechsler, Rolf

“…Nowadays, a variety of multipliers are used in different computationally intensive industrial applications. Most of these multipliers are highly parallelized…”
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BP-NTT: Fast and Compact in-SRAM Number Theoretic Transform with Bit-Parallel Modular Multiplication Autor Zhang, Jingyao, Imani, Mohsen, Sadredini, Elaheh

“… However, costly division operations and complex data dependencies make efficient and flexible hardware design to be challenging, especially on resource-constrained edge devices…”
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AccALS: Accelerating Approximate Logic Synthesis by Selection of Multiple Local Approximate Changes Autor Wang, Xuan, Tao, Sijun, Zhu, Jingjing, Shi, Yiyu, Qian, Weikang

“… To automatically synthesize approximate circuits, many iterative approximate logic synthesis (ALS) methods have been proposed…”
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BBAL: A Bidirectional Block Floating Point-Based Quantisation Accelerator for Large Language Models Autor Han, Xiaomeng, Cheng, Yuan, Wang, Jing, Lu, Junyang, Wang, Hui, Zhang, X.x., Xu, Ning, Yang, Dawei, Jiang, Zhe

“…Large language models (LLMs), with their billions of parameters, pose substantial challenges for deployment on edge devices, straining both memory capacity and…”
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Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like Method Autor Xie, Jiafeng, He, Pengzhou, Wen, Wujie

“…: (i) an algorithm-hardware co-design driven derivation of the proposed LUT-like method is provided detailedly for the key arithmetic of the BRLWE scheme; (ii…”
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AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity Autor Lin, Xiaolong, Li, Gang, Liu, Zizhao, Liu, Yadong, Zhang, Fan, Song, Zhuoran, Jing, Naifeng, Liang, Xiaoyao

“…Bit-sparsity has shown its promise in CNN acceleration. However, prior bit-sparse accelerators have two drawbacks: 1) a large number of zero values are…”
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Uint-Packing: Multiply Your DNN Accelerator Performance via Unsigned Integer DSP Packing Autor Zhang, Jingwei, Zhang, Meng, Cao, Xinye, Li, Guoqing

“…DSP blocks are undoubtedly efficient solutions for implementing multiply-accumulate (MAC) operations on FPGA. Since DSP resources are scarce in FPGA, the…”
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Comparison-Free Bit-Stream Generation for Cost-Efficient Unary Computing Autor Banitaba, Faeze S., Jalilvand, Amir Hossein, Najafi, M. Hassan, Aygun, Sercan

“…Today, unconventional hardware design techniques based on simple data representations are receiving more and more…”
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Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers Autor Leon, Vasileios, Asimakopoulos, Konstantinos, Xydis, Sotirios, Soudris, Dimitrios, Pekmestzi, Kiamal

“… In this paper, targeting multiplication circuits, i.e., the energy-hungry counterpart of hardware accelerators, an extensive exploration of the error- energy trade-off…”
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