Search Results - Hardware Integrated circuits Logic circuits Arithmetic AND datapath circuits

A new stochastic computing multiplier with application to deep convolutional neural networks by Hyeonuk Sim, Jongeun Lee

“…Stochastic computing (SC) allows for extremely low cost and low power implementations of common arithmetic operations…”
Get full text

Architectural-space exploration of approximate multipliers by Rehman, Semeen, El-Harouni, Walaa, Shafique, Muhammad, Kumar, Akash, Henkel, Jorg

“…This paper presents an architectural-space exploration methodology for designing approximate multipliers. Unlike state-of-the-art, our methodology generates…”
Get full text

Bit-pragmatic deep neural network computing by Albericio, Jorge, Delmás, Alberto, Judd, Patrick, Sharify, Sayeh, O'Leary, Gerard, Genov, Roman, Moshovos, Andreas

“…Deep Neural Networks expose a high degree of parallelism, making them amenable to highly data parallel architectures. However, data-parallel architectures…”
Get full text

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks by Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee, Kiyoung Choi

“… The approach allows an easy implementation of early decision termination with a fixed hardware design by exploiting the progressive precision characteristics of stochastic computing, which was not…”
Get full text

A low latency generic accuracy configurable adder by Shafique, Muhammad, Ahmad, Waqas, Hafiz, Rehan, Henkel, Jorg

“… An error correction unit is integrated to provide accurate results for cases where high accuracy is required…”
Get full text

Measurement-based uncomputation of quantum circuits for modular arithmetic by Luongo, Alessandro, Miti, Antonio Michele, Narasimhachar, Varun, Sireesh, Adithya

“…% for modular adders based on the architecture of [2]. Our results have the potential to improve other circuits for modular arithmetic, such as modular multiplication…”
Get full text

Logic Synthesis for Digital In-Memory Computing by Haq Rashed, Muhammad Rashedul, Kumar Jha, Sumit, Ewetz, Rickard

“… State-of-the-art digital in-memory computing schemes rely on manually decomposing arithmetic operations into in-memory compute kernels…”
Get full text

Equivalence among stochastic logic circuits and its application by Te-Hsuan Chen, Hayes, John P.

“… It implements arithmetic operations by extremely simple and low-power hardware. Despite major new applications, SC's theory and design requirements are poorly understood…”
Get full text

Stochastic circuits for real-time image-processing applications by Alaghi, Armin, Li, Cheng, Hayes, John P.

“… We show how stochastic circuits can be integrated at the pixel level with image sensors, thus supporting efficient real-time (pre…”
Get full text

An Enhanced Data Packing Method for General Matrix Multiplication in Brakerski/Fan-Vercauteren Scheme by Meng, Xiangchen, Tan, Yan, Jiang, Zijun, Lyu, Yangdi

“… Furthermore, we design specialized hardware…”
Get full text

Precon: A Precision-Convertible Architecture for Accelerating Quantized Deep Learning Models across Various Domains Including LLMs by Park, Jongwoo, Kim, Hyeonseong, Han, Jiyun, Choi, Seungkyu

“… By enabling on-the-fly switching between half-float (FP16) decoding and integer (INT) decomposition, the design effectively supports INT4-FP16, INT4-INT4, and INT4INT8 arithmetic within shared logic…”
Get full text

PolyCleaner: Clean your Polynomials before Backward Rewriting to verify Million-gate Multipliers by Mahzoon, Alireza, Grosse, Daniel, Drechsler, Rolf

“…Nowadays, a variety of multipliers are used in different computationally intensive industrial applications. Most of these multipliers are highly parallelized…”
Get full text

BP-NTT: Fast and Compact in-SRAM Number Theoretic Transform with Bit-Parallel Modular Multiplication by Zhang, Jingyao, Imani, Mohsen, Sadredini, Elaheh

“… However, costly division operations and complex data dependencies make efficient and flexible hardware design to be challenging, especially on resource-constrained edge devices…”
Get full text

Uint-Packing: Multiply Your DNN Accelerator Performance via Unsigned Integer DSP Packing by Zhang, Jingwei, Zhang, Meng, Cao, Xinye, Li, Guoqing

“…DSP blocks are undoubtedly efficient solutions for implementing multiply-accumulate (MAC) operations on FPGA. Since DSP resources are scarce in FPGA, the…”
Get full text

AccALS: Accelerating Approximate Logic Synthesis by Selection of Multiple Local Approximate Changes by Wang, Xuan, Tao, Sijun, Zhu, Jingjing, Shi, Yiyu, Qian, Weikang

“… To automatically synthesize approximate circuits, many iterative approximate logic synthesis (ALS) methods have been proposed…”
Get full text

Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like Method by Xie, Jiafeng, He, Pengzhou, Wen, Wujie

“…: (i) an algorithm-hardware co-design driven derivation of the proposed LUT-like method is provided detailedly for the key arithmetic of the BRLWE scheme; (ii…”
Get full text

BBAL: A Bidirectional Block Floating Point-Based Quantisation Accelerator for Large Language Models by Han, Xiaomeng, Cheng, Yuan, Wang, Jing, Lu, Junyang, Wang, Hui, Zhang, X.x., Xu, Ning, Yang, Dawei, Jiang, Zhe

“…Large language models (LLMs), with their billions of parameters, pose substantial challenges for deployment on edge devices, straining both memory capacity and…”
Get full text

AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity by Lin, Xiaolong, Li, Gang, Liu, Zizhao, Liu, Yadong, Zhang, Fan, Song, Zhuoran, Jing, Naifeng, Liang, Xiaoyao

“…Bit-sparsity has shown its promise in CNN acceleration. However, prior bit-sparse accelerators have two drawbacks: 1) a large number of zero values are…”
Get full text

Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers by Leon, Vasileios, Asimakopoulos, Konstantinos, Xydis, Sotirios, Soudris, Dimitrios, Pekmestzi, Kiamal

“… In this paper, targeting multiplication circuits, i.e., the energy-hungry counterpart of hardware accelerators, an extensive exploration of the error- energy trade-off…”
Get full text

Don't-Care Aware ESOP Extraction via Reduced Decomposition-Tree Exploration by Wei, Chun-Yu, Jiang, Jie-Hong R.

“…Exclusive-OR Sum-of-Products expressions (ESOPs) are vital for circuit synthesis of arithmetic functions and emerging technologies…”
Get full text