Výsledky vyhledávání - Hardware Hardware validation Functional verification

RFUZZ: Coverage-Directed Fuzz Testing of RTL on FPGAs Autor Laeufer, Kevin, Koenig, Jack, Kim, Donggyu, Bachrach, Jonathan, Sen, Koushik

“…Dynamic verification is widely used to increase confidence in the correctness of RTL circuits during the pre-silicon design phase…”
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An Efficient Algorithm for Sparse Quantum State Preparation Autor Gleinig, Niels, Hoefler, Torsten

“…Generating quantum circuits that prepare specific states is an essential part of quantum compilation. Algorithms that solve this problem for general states…”
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EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components Autor Wang, Mingjun, Wang, Hui, Mu, Jianan, Zhang, Xinyu, Sun, Bin, Wen, Yihan, Liu, Zizhen, Gu, Feng, Gao, Jun, Liang, Shengwen, Ye, Jing, Li, Xiaowei, Li, Huawei

“…As functional safety of electronic chips gains importance in autonomous vehicles and aerospace, standards like ISO 26262 mandate high diagnostic coverage, requiring extensive gate-level fault simulations…”
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Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation Autor Tsai, Yuan-Hung, Jiang, Jie-Hong R., Jhang, Chiao-Shan

“… Quantum circuit simulation plays a key role in the toolchain of quantum hardware and software development…”
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EPIC: Error PredIction and Correction for Power-Efficient Voltage Underscaling Multiply-Accumulate Unit Autor Wu, Tongjing, Hu, Xiaolu, Li, Tong, Liu, Siting, Wang, Hui, He, Weifeng, Mao, Zhigang, Jiang, Honglan

“… A prediction bits searching algorithm is proposed to enhance the prediction accuracy with low hardware cost, resulting in up to 100% accuracy…”
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Leveraging Critical Proof Obligations for Efficient IC3 Verification Autor Zhu, Lingfeng, Zhang, Xindi, Li, Yongjian, Cai, Shaowei

“…IC3 and its variants are SAT-based model-checking methods that play a critical role in hardware verification…”
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Generative Model Based Standard Cell Timing Library Characterization Autor Wu, Hao-Yu, Chang, Hsin-Tzu, Ding, Shiuan-Yun, Jiang, Iris Hui-Ru, Tsao, Benson, Wu, Vinson, Shih, Wei-Kai

“…Accurate cell timing characterization is essential, on which static timing analysis relies to verify timing performance and ensure design robustness across…”
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Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation Autor Liang, Rongjian, Pinckney, Nathaniel, Chai, Yuji, Ren, Haoxin, Khailany, Brucek

“…Functional coverage closure is an important but RTL simulation intensive aspect of constrained random verification…”
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Swift or Exact? Boosting Efficient Microarchitecture DSE via Multi-fidelity Partial Order Prediction Autor Liu, Hang, Geng, Hao, He, Zhuolun, Sun, Qi, Zhuo, Cheng

“…A significant challenge in microarchitecture design space exploration (DSE) lies in the time-intensive synthesis and simulation process, making rapid design…”
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Late Breaking Results: Opera: An Open and Efficient Platform for Data-driven Synthesis of Analog Circuits Autor Wang, Shikai, Hu, Yaolong, Yi, Zhiqiang, Chi, Taiyun, Cao, Weidong

“…The front-end synthesis of analog circuits has been a long-standing challenge since the advent of integrated circuits. Many methods, ranging from conventional…”
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Revisiting and Improving Retrieval-Augmented Deep Assertion Generation Autor Sun, Weifeng, Li, Hongyan, Yan, Meng, Lei, Yan, Zhang, Hongyu

“…Unit testing validates the correctness of the unit under test and has become an essential activity in software development process. A unit test consists of a…”
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SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation Autor Yu, Ziyang, Xu, Peng, Wang, Zixiao, Zhu, Binwu, Wang, Qipan, Lin, Yibo, Wang, Runsheng, Yu, Bei, Wong, Martin

“…The post-exposure bake (PEB) process is a critical step in semiconductor lithography, directly impacting resist profile accuracy and circuit pattern fidelity…”
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A Cutting-Edge Parallel Solver for Scalable Power Grid Analysis Using Nested Domain Decomposition Autor Song, Jianfei, Yang, Xiaoyu, Jin, Zhou, Zhuo, Cheng

“…As transistor scaling approaches sub-5 nm technologies, power distribution networks (PDNs) in integrated circuits have grown increasingly complex, with…”
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MemSens: Significantly Reducing Memory Overhead in Adjoint Sensitivity Analysis Using Novel Error-Bounded Lossy Compression Autor Li, Chenxi, Feng, Yihang, Deng, Fuxing, Tao, Dingwen, Liu, Weifeng, Jin, Zhou

“…Adjoint sensitivity analysis is an exceptionally efficient method for computing the gradient of an objective function with respect to given parameters, playing a crucial role in modern circuit design and verification…”
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HPIM-NoC: A Priori-Knowledge-Based Optimization Framework for Heterogeneous PIM-Based NoCs Autor Yuan, Shuai, Cai, Angxin, Lin, Qiushi, Wang, Guoxing, Wang, Yu, Zhu, Zhenhua, Sun, Yanan

“…Network-on-Chip (NoC) accelerators with heterogeneous Processing-in-Memory (PIM) cores achieve superior performance than homogeneous ones for neural networks…”
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GSIM: Accelerating RTL Simulation for Large-Scale Designs Autor Chen, Lu, Zhao, Dingyi, Yu, Zihao, Sun, Ninghui, Bao, Yungang

“…Register Transfer Level (RTL) simulation is widely used in design space exploration, verification, debugging, and preliminary performance evaluation for hardware design…”
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Bayesian Inference Based Robust Computing on Memristor Crossbar Autor Gao, Di, Huang, Qingrong, Zhang, Grace Li, Yin, Xunzhao, Li, Bing, Schlichtmann, Ulf, Zhuo, Cheng

“… In this paper, we propose a unified Bayesian inference based framework which connects hardware variations and algorithmic training together for robust computing on memristor crossbars…”
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SimPhony: A Device-Circuit-Architecture Cross-Layer Modeling and Simulation Framework for Heterogeneous Electronic-Photonic AI System Autor Yin, Ziang, Zhang, Meng, Gangi, Nicholas, Huang, Rena, Zhang, Jeff, Gu, Jiaqi

“… The lack of a flexible, accurate, fast, and easy-to-use EPIC AI system simulation framework significantly limits the exploration of hardware innovations and system evaluations on common benchmark…”
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Accelerating design-technology co-development using neural compact modeling and data-driven SPICE simulation Autor Lee, Yongjeong, Lee, Seungsoo, Kim, Jeongyeol, Choi, Jungyun, Li, Zhaojie, Wu, Dehuang, Wang, Joddy

“…This paper proposes a new design-technology cooptimization framework that expedites circuit optimization by utilizing the neural compact modeling (NCM) and a…”
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INSIGHT: A Universal Neural Simulator Framework for Analog Circuits with Autoregressive Transformers Autor Poddar, Souradip, Oh, Youngmin, Lai, Yao, Zhu, Hanqing, Hwang, Bosun, Pan, David Z.

“…The compute-intensive nature of SPICE simulations hinders effective analog design automation. This paper introduces INSIGHT, a data-efficient, adaptive,…”
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