Search Results - Hardware Electronic design automation Logic synthesis Circuit optimization~

Scalable Optimal Layout Synthesis for NISQ Quantum Processors by Lin, Wan-Hsuan, Kimko, Jason, Tan, Bochen, Bjorner, Nikolaj, Cong, Jason

“…Due to its effect on the success rate of a quantum circuit, quantum layout synthesis is a crucial step for circuit compilation…”
Get full text

Local Bayesian Optimization For Analog Circuit Sizing by Touloupas, Konstantinos, Chouridis, Nikos, Sotiriadis, Paul P.

“…This paper proposes a Bayesian Optimization (BO) algorithm to handle large-scale analog circuit sizing…”
Get full text

An Efficient Algorithm for Sparse Quantum State Preparation by Gleinig, Niels, Hoefler, Torsten

“…Generating quantum circuits that prepare specific states is an essential part of quantum compilation…”
Get full text

Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision by Fu, Rongliang, Zhang, Ran, Zheng, Ziyang, Shi, Zhengyuan, Pu, Yuan, Huang, Junying, Xu, Qiang, Ho, Tsung-Yi

“…Hybrid optimization is an emerging approach in logic synthesis, focusing on applying diverse optimization methods to different parts of a logic circuit…”
Get full text

Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving by Shi, Zhengyuan, Tang, Tiebing, Zhu, Jiaying, Khan, Sadaf, Zhen, Hui-Ling, Yuan, Mingxuan, Chu, Zhufei, Xu, Qiang

“…) problem, plays a critical role in integrated circuit design and verification. However, existing SAT solvers, optimized for Conjunctive Normal Form (CNF…”
Get full text

RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning by Lu, Yi-Chen, Nath, Siddhartha, Khandelwal, Vishal, Lim, Sung Kyu

“…Gate sizing for timing optimization is performed extensively throughout electronic design automation (EDA) flows…”
Get full text

Logic Restructuring with Preserved Logic Blocks by Lee, Siang-Yun, Riener, Heinz, Richter, Sascha, Sood, Ankush

“…) by decomposing blocks of logic that could have been mapped into complex cells. Besides, it is also of practical interest to model and preserve some special logic components, such as the enable logic of flops, during optimization…”
Get full text

A Post-Implementation Performance Prediction Method with HLS Optimization Directives by Zhu, Jingyu, Ding, Yan, Xiao, Lu, Li, Kenli, Liu, Chubo, Xiao, Zheng

“…High-Level Synthesis (HLS) offers various optimization directives that enable designers to flexibly adjust hardware microarchitecture…”
Get full text

Efficient Continuous Logic Optimization with Diffusion Model by Ouyang, Yikang, Yu, Xiaofei, Zhu, Jiadong, Chen, Tinghuan, Ma, Yuzhe

“…The logic synthesis optimization flow is crucial to the quality of results (QoR), which applies a sequence of transformations to a design…”
Get full text

ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring by Tsaras, Dimitris, Li, Xing, Chen, Lei, Xie, Zhiyao, Yuan, Mingxuan

“…In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits…”
Get full text

Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard Cells by Ahn, Jaehoon, Kim, Taewhan

“… However, the layout synthesis of CFET based standard cells and its use in physical design implementation are not fully compatible with the effective exploitation of backside interconnects…”
Get full text

MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing by Li, Wangzhen, Meng, Yuan, Lyu, Ruiyu, Yan, Changhao, Zhu, Keren, Bi, Zhaori, Zhou, Dian, Zeng, Xuan

“…Numeric optimization methods are widely utilized to tackle complex analog circuit sizing problems, where the challenges include expensive simulations, non-linearity, and high parameter dimensionality…”
Get full text

EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis by Tang, Ruofei, Zhu, Xuliang, Zhang, Xinyi, Chen, Lei, Li, Xing, Yuan, Mingxuan, Xu, Jianliang

“… Decomposition-based logic synthesis yields high-quality results and is particularly effective when combined with small-window optimization methods in Gate-Inverter Graphs (GIG…”
Get full text

SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding by Li, Chengxi, Sun, Yang, Chen, Lei, Wang, Yiwen, Yuan, Mingxuan, Young, Evangeline F.Y.

“…This paper proposes smaRTLy: a new optimization technique for multiplexers in Register-Transfer Level (RTL) logic synthesis…”
Get full text

Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search by Ye, Yuyang, Hu, Xiangfei, Liu, Yuchen, Xu, Peng, Gong, Yu, Chen, Tinghuan, Yan, Hao, Yu, Bei, Shi, Longxing

“…Approximate Logic Synthesis (ALS) is an automated technique designed for error-tolerant applications, optimizing delay, area, and power under specified error constraints…”
Get full text

Batch Sequential Black-box Optimization with Embedding Alignment Cells for Logic Synthesis by Feng, Chang, Lyu, Wenlong, Chen, Zhitang, Ye, Junjie, Yuan, Mingxuan, Hao, Jianye

“… In this paper, we formulate the logic synthesis design space exploration as a conditional sequence optimization problem, where at each transformation step, an optimization operator is selected…”
Get full text

Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization Problems by Qian, Yu, Huang, Xianmin, Wang, Ranran, Yang, Zeyu, Zhou, Min, Kampfe, Thomas, Zhuo, Cheng, Yin, Xunzhao

“…Combinatorial optimization problems (COPs) are crucial in many applications but are computationally demanding…”
Get full text

A Fast, Iterative Clock Skew Scheduling Algorithm with Dynamic Sequential Graph Extraction by Chen, Shijian, Qiu, Yihang, Xie, Biwei, Chen, Mingyu, Li, Xingquan

“…Clock skew scheduling (CSS) is a well-known technique that improves design timing slack by adjusting clock latency to flipflops…”
Get full text

Approximate Equivalence Checking of Noisy Quantum Circuits by Hong, Xin, Ying, Mingsheng, Feng, Yuan, Zhou, Xiangzhen, Li, Sanjiang

“…We study the fundamental design automation problem of equivalence checking in the NISQ…”
Get full text

A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis by Jiang, Xun, Lu, Haoran, Zhao, Yuxuan, Wang, Jiarui, Guo, Zizheng, Wu, Heng, Yu, Bei, Lim, Sung Kyu, Wang, Runsheng, Huang, Ru, Lin, Yibo

“…). However, these works lack a systematic perspective on design resource allocation and multi-objective optimization…”
Get full text