Search Results - Computer systems organization Architectures Serial architectures Pipeline computing

Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation by Tagata, Hiroto, Sato, Takashi, Awano, Hiromitsu

“… Previous research has employed large analog computing circuits to convert inputs into LUT addresses, which presents challenges to area efficiency and computational accuracy…”
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Bit-level Perceptron Prediction for Indirect Branches by Garza, Elba, Mirbagher-Ajorpaz, Samira, Khan, Tahsin Ahmad, Jimenez, Daniel A.

“…Modern software uses indirect branches for various purposes including, but not limited to, virtual method dispatch and implementation of switch statements…”
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UpPipe: A Novel Pipeline Management on In-Memory Processors for RNA-seq Quantification by Chen, Liang-Chi, Ho, Chien-Chung, Chang, Yuan-Hao

“…, memory wall problem on the conventional architecture. As the first publicly commercial processing-in-memory (PIM…”
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Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution by Bera, Rahul, Ranganathan, Adithya, Rakshit, Joydeep, Mahto, Sujit, Nori, Anant V., Gaur, Jayesh, Olgun, Ataberk, Kanellopoulos, Konstantinos, Sadrosadati, Mohammad, Subramoney, Sreenivas, Mutlu, Onur

“… (even on a correct prediction), which consumes hard-to-scale pipeline resources that otherwise could have been used to execute other load instructions…”
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MixPipe: Efficient Bidirectional Pipeline Parallelism for Training Large-Scale Models by Zhang, Weigang, Zhou, Biyu, Tang, Xuehai, Wang, Zhaoxing, Hu, Songlin

“… Recently, bidirectional pipeline parallelism has been recognized as an effective approach for improving training throughput…”
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Buffer Prospector: Discovering and Exploiting Untapped Buffer Resources in Many-Core DNN Accelerators by Wei, Yuchen, Cai, Jingwei, Gao, Mingyu, Peng, Sen, Wu, Zuotong, Shi, Guiming, Ma, Kaisheng

“…In large-scale DNN inference accelerators, the many-core architecture has emerged as a predominant design, with layer-pipeline (LP…”
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Alternate Path μ-op Cache Prefetching by Singh, Sawan, Perais, Arthur, Jimborean, Alexandra, Ros, Alberto

“…Datacenter applications are well-known for their large code footprints. This has caused frontend design to evolve by implementing decoupled fetching and large…”
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Alternate Path Fetch by Deshmukh, Aniket, Cai, Lingzhe Chester, Patt, Yale N.

“… This requires building wider pipelines with more accurate branch predictors. However, scaling the pipeline width is becoming more challenging due to limitations…”
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Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters by Cavalcante, Matheus, Wuthrich, Domenic, Perotti, Matteo, Riedel, Samuel, Benini, Luca

“…While parallel architectures based on clusters of Processing Elements (PEs) sharing L1 memory are widespread, there is no consensus on how lean their PE…”
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UDP: Utility-Driven Fetch Directed Instruction Prefetching by Oh, Surim, Xu, Mingsheng, Khan, Tanvir Ahmed, Kasikci, Baris, Litz, Heiner

“… However, our study shows that existing implementations still fall far short of an ideal system with a perfect instruction cache…”
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X-Layer: Building Composable Pipelined Dataflows for Low-Rank Convolutions by Vedula, Naveen, Hojabr, Reza, Khonsari, Ahmad, Shriraman, Arrvindh

“… X-Layer decouples the nested loops in a pipeline and combines them to create a common outer dataflow and several inner dataflows…”
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AVM-BTB: Adaptive and Virtualized Multi-level Branch Target Buffer by Liu, Yunzhe, Li, Xinyu, Zhang, Tingting, Liu, Tianyi, Guo, Qi, Zhang, Fuxin, Wang, Jian

“…Branch Target Buffer (BTB) plays an important role in modern processors. It is used to identify branches in the instruction stream and predict branch targets…”
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PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis by Li, Rui, Berkley, Lincoln, Manohar, Rajit

“…Dynamically scheduled high-level synthesis (HLS) is an approach to HLS that maps programs into dataflow circuits. These circuits use distributed control for…”
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Load value prediction via path-based address prediction: avoiding mispredictions due to conflicting stores by Sheikh, Rami, Cain, Harold W., Damodaran, Raguram

“… Challenge #2: value mispredictions trigger costly pipeline flushes. To minimize the number of pipeline flushes, value predictors employ stringent, yet necessary, high confidence requirements to guarantee high prediction accuracy…”
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Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed by Liu, Chang, Lyu, Yongqiang, Wang, Haixia, Qiu, Pengfei, Ju, Dapeng, Qu, Gang, Wang, Dongsheng

“…Memory Disambiguation Unit (MDU) is widely used on modern processors to speculatively execute load instructions and improve pipeline performance…”
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Pipelining a triggered processing element by Repetti, Thomas J., Cerqueira, João P., Kim, Martha A., Seok, Mingoo

“… We propose two new techniques to mitigate pipeline hazards particular to spatial accelerators and non-program-counter architectures, evaluating them using in-vivo performance counters from an FPGA…”
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SMT-COP: Defeating Side-Channel Attacks on Execution Units in SMT Processors by Townley, Daniel, Ponomarev, Dmitry

“…) architectures from the security standpoint. To address this problem, we propose SMT-COP-a system that eliminates all known side-channels through shared execution logic, including ports and functional units, on SMT processors…”
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Filter Caching for Free: The Untapped Potential of the Store-Buffer by Alves, Ricardo, Ros, Alberto, Black-Schaffer, David, Kaxiras, Stefanos

“…Modern processors contain store-buffers to allow stores to retire under a miss, thus hiding store-miss latency. The store-buffer needs to be large (for…”
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FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template by Choudhary, Niket K., Wadhavkar, Salil V., Shah, Tanmay A., Mayukh, Hiran, Gandhi, Jayneel, Dwiel, Brandon H., Navada, Sandeep, Najaf-abadi, Hashem H., Rotenberg, Eric

“…: superscalar width, pipeline depth, and sizes of structures for extracting instruction-level parallelism (ILP…”
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Sparse-T: Hardware accelerator thread for unstructured sparse data processing by Vasireddy, Pranathi, Kavi, Krishna, Mehta, Gayatri

“…Sparse matrix-dense vector (SpMV) multiplication is inherent in most scientific, neural networks and machine learning algorithms. To efficiently exploit…”
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