Search Results - Computer system organization Architectures Other architectures Reconfigurable computing*

DRISA: a DRAM-based Reconfigurable In-Situ Accelerator by Li, Shuangchen, Niu, Dimin, Malladi, Krishna T., Zheng, Hongzhong, Brennan, Bob, Xie, Yuan

“… To address the challenge, we propose DRISA, a DRAM-based Reconfigurable In-Situ Accelerator architecture, to provide both powerful computing capability and large memory capacity/bandwidth…”
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Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks by Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong

“… Second, we design Caffeine with the goal to maximize the underlying FPGA computing and bandwidth…”
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Stream-dataflow acceleration by Nowatzki, Tony, Gangadhar, Vinay, Ardalani, Newsha, Sankaralingam, Karthikeyan

“…) are insufficient, as evidenced by the order-of-magnitude improvements and industry adoption of application and domain-specific accelerators in important areas like machine learning, computer vision and big data…”
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Maximizing CNN accelerator efficiency through resource partitioning by Yongming Shen, Ferdman, Michael, Milder, Peter

“…Convolutional neural networks (CNNs) are revolutionizing machine learning, but they present significant computational challenges. Recently, many FPGA-based…”
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SODA: Stencil with Optimized Dataflow Architecture by Chi, Yuze, Cong, Jason, Wei, Peng, Zhou, Peipei

“… In this paper we present SODA, an automated framework for implementing Stencil algorithms with Optimized Dataflow Architecture on FPGAs…”
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Qubit Mapping for Reconfigurable Atom Arrays by Tan, Bochen, Bluvstein, Dolev, Lukin, Mikhail D., Cong, Jason

“…Because of the largest number of qubits available, and the massive parallel execution of entangling two-qubit gates, atom arrays is a promising platform for quantum computing…”
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FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching by Tong, Jianming, Itagi, Anirudh, Chatarasi, Prasanth, Krishna, Tushar

“…The inference of ML models composed of diverse structures, types, and sizes boils down to the execution of different dataflows (i.e. different tiling,…”
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HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing by Huang, Jinghan, Lou, Jiaqi, Vanavasam, Srikar, Kong, Xinhao, Ji, Houxiang, Jeong, Ipoom, Zhuo, Danyang, Lee, Eun Kyung, Kim, Nam Sung

“… With such a processor, the SNIC has promised to notably improve the system-wide energy efficiency of datacenter servers…”
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MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition by Qin, Yubin, Wang, Yang, Zhao, Zhiren, Yang, Xiaolong, Zhou, Yang, Wei, Shaojun, Hu, Yang, Yin, Shouyi

“…Large language models (LLMs) have been showing surprising performance in processing language tasks, bringing a new prevalence to deploy LLM from cloud to edge…”
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TGPA: Tile-Grained Pipeline Architecture for Low Latency CNN Inference by Wei, Xuechao, Liang, Yun, Li, Xiuhong, Yu, Cody Hao, Zhang, Peng, Cong, Jason

“…FPGAs are more and more widely used as reconfigurable hardware accelerators for applications leveraging convolutional neural networks (CNNs) in recent years…”
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Understanding and optimizing asynchronous low-precision stochastic gradient descent by De Sa, Christopher, Feldman, Matthew, Re, Christopher, Olukotun, Kunle

“…Stochastic gradient descent (SGD) is one of the most popular numerical algorithms used in machine learning and other domains. Since this is likely to continue…”
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Map-and-Conquer: Energy-Efficient Mapping of Dynamic Neural Nets onto Heterogeneous MPSoCs by Bouzidi, Halima, Odema, Mohanad, Ouarnoughi, Hamza, Niar, Smail, Al Faruque, Mohammad Abdullah

“… To date, the mapping strategies of neural networks (NNs) onto such systems are yet to exploit the full potential of processing parallelism, made possible through both the intrinsic NNs' structure and underlying hardware composition…”
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MASR: A Modular Accelerator for Sparse RNNs by Gupta, Udit, Reagen, Brandon, Pentecost, Lillian, Donato, Marco, Tambe, Thierry, Rush, Alexander M., Wei, Gu-Yeon, Brooks, David

“… In this paper we present MASR, a principled and modular architecture that accelerates bidirectional RNNs for on-chip ASR…”
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CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics by Feng, Siying, Sun, Jiawen, Pal, Subhankar, He, Xin, Kaszyk, Kuba, Park, Dong-hyeon, Morton, Magnus, Mudge, Trevor, Cole, Murray, O'Boyle, Michael, Chakrabarti, Chaitali, Dreslinski, Ronald

“… reconfiguration as a synergistic solution to accelerate SpMV-based graph analytics algorithms. Building on previously proposed general-purpose reconfigurable hardware…”
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MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models by Lu, Shaoqiang, Yu, Xuliang, Zhao, Tiandong, Miao, Siyuan, Sheng, Xinsong, Wu, Chen, Zhao, Liang, Lin, Ting-Jung, He, Lei

“…State-space models (SSMs), such as Mamba, have emerged as a promising alternative to Transformers. However, the recently developed Mamba2, based on state space…”
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NTT-PIM: Row-Centric Architecture and Mapping for Efficient Number-Theoretic Transform on PIM by Park, Jaewoo, Lee, Sugil, Lee, Jongeun

“…Recently DRAM-based PIMs (processing-in-memories) with unmodified cell arrays have demonstrated impressive performance for accelerating AI applications…”
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DRAFT: Decoupling Backpropagation from Pre-trained Backbone for Efficient Transformer Fine-Tuning on Edge by Huang, Zhirui, Liu, Shiwei, Zhu, Haozhe, Liu, Qi, Chen, Chixiao

“…). The existing fine-tuning techniques require the BP through the massive pre-trained backbone weights for computing the input gradient, resulting in significant computing overhead and memory footprint…”
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RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU by Jeong, Geonhwa, Qin, Eric, Samajdar, Ananda, Hughes, Christopher J., Subramoney, Sreenivas, Kim, Hyesoon, Krishna, Tushar

“…As AI-based applications become pervasive, CPU vendors are starting to incorporate matrix engines within the datapath to boost efficiency. Systolic arrays have…”
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Buffer Prospector: Discovering and Exploiting Untapped Buffer Resources in Many-Core DNN Accelerators by Wei, Yuchen, Cai, Jingwei, Gao, Mingyu, Peng, Sen, Wu, Zuotong, Shi, Guiming, Ma, Kaisheng

“…In large-scale DNN inference accelerators, the many-core architecture has emerged as a predominant design, with layer-pipeline (LP…”
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Heterogeneous Reconfigurable Accelerators: Trends and Perspectives by Luk, Wayne

“…Heterogeneity and reconfigurability have both been adopted by accelerators to improve their flexibility and efficiency for a wide variety of applications, from cloud computing to embedded systems…”
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