Search Results - 3-D processor array

Efficient 3-D Processor Array Reconfiguration Algorithms Based on Bucket Effect by Ding, Hao, He, Yanlong, Zhai, Zhongyi, Li, Zhi, Qian, Junyan, Zhao, Lingzhong

“…With the progressive augmentation of the density of 3-D processor arrays, some processor elements (PEs…”
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Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays by Qian, Junyan, Ding, Hao, Xiao, Hanpeng, Zhou, Zhide, Zhao, Lingzhong, Zhai, Zhongyi

“…In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible…”
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An Alternative Mapping of 3-D Space onto Processor Arrays by Gil, Joseph, Wagner, Alan

“… space onto low degree processor arrays. We show that the woven mesh can be embedded with dilation 2 and congestion 4 onto a 3-D mesh…”
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High resolution and frame rate image signal processor array design for 3-D imager by Chang-Hsin Cheng, Hsien-Ching Hsieh, Tso-Yi Fan, Wei-Xiang Tang, Chung-Kai Liu, Po-Han Huang

“…This paper presents a high resolution and frame rate image signal processor (ISP) array design for three-dimensional…”
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A Fast Fourier-Based Near-Field 3-D Imaging Algorithm for MIMO Array by Hu, Ze, Su, Tao, Xu, Dan, Pang, Guanghui, Gini, Fulvio

“… In this article, a fast Fourier-based near-field 3-D imaging algorithm for the MIMO array is proposed, and it requires less hardware processor memory capacity…”
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Mapping regular algorithms onto multilayered 3-D reconfigurable processor array by Plaks, T.P.

“…Extends the systolic array approach and presents a 3D reconfigurable array processor with a method for mapping algorithms onto this processor…”
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IBM (IBM) issued patent titled "Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array"

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Fast Implementation of 3-D Digital Filters Via Systolic Array Processors by Mertzios, B. G., Venetsanopoulos, A. N.

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US Patent Issued to International Business Machines on Aug. 11 for "Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array" (California, New York, Vermont, Texas Inventors)

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High-Resolution Imager Based on Time-to-Space Conversion by Lusardi, Nicola, Garzetti, Fabio, Costa, Andrea, Cautero, Marco, Corna, Nicola, Ronconi, Enrico, Brajnik, Gabriele, Stebel, Luigi, Sergo, Rudi, Cautero, Giuseppe, Carrato, Sergio, Geraci, Angelo

“… The system uses cross delay line (CDL) detectors for particle identification and a fully configurable digital processor based on field programmable gate arrays (FPGAs…”
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US Patent Issued to International Business Machines on April 10 for "Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array" (New York Inventor)

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US Patent Issued to International Business Machines on June 14 for "Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array" (New York Inventor)

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Design of Ternary Neural Network With 3-D Vertical RRAM Array by Li, Zhiwei, Chen, Pai-Yu, Xu, Hui, Yu, Shimeng

“… This paper aims to extend such 2-D cross-point array to 3-D vertical array for storing and computing the large-scale weight matrices in the neural network…”
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3-D NAND Technology Achievements and Future Scaling Perspectives by Goda, Akira

“… ) in the recent five years. The increase of word-line (WL) stacking from 24 to 128 layers, the scaling of bits per cell from 2 to 3 bits/cell and 4 bits/cell, and a CMOS under array technology enabled this successful 3-D NAND density scaling…”
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An Energy-Efficient Unstructured Sparsity-Aware Deep SNN Accelerator With 3-D Computation Array by Fang, Chaoming, Shen, Ziyang, Wang, Zongsheng, Wang, Chuanqing, Zhao, Shiqi, Tian, Fengshi, Yang, Jie, Sawan, Mohamad

“…: a 3-D computation array that allows parallel computation of multiple timesteps to maximize…”
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High-Density 3-D NAND Cell Array Design With Hybrid Bonding by Lee, Seungmin, Lim, Joonsung, Kim, Jun Hyoung, Cho, Sunghwan, Lee, Yong Kyu, Choi, Byoungdeog

“…In this study, we propose a novel cell array structure suitable for hybrid bonding technology, which is considered one of the promising future technologies in 3-D NAND architecture…”
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Drain-Erase Scheme in Ferroelectric Field Effect Transistor-Part II: 3-D-NAND Architecture for In-Memory Computing by Wang, Panni, Shim, Wonbo, Wang, Zheng, Hur, Jae, Datta, Suman, Khan, Asif Islam, Yu, Shimeng

“…) devices with the potential for in-memory computing. In this two-part article, we explore the feasibility of the FeFET-based 3-D NAND architecture for both in situ training and inference…”
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A 29-Gb/mm2 1-Tb 3-b/Cell 3-D Flash Memory With CMOS Direct Bonded Array (CBA) Technology by Yanagidaira, Kosuke, Sako, Mario, Hirashima, Yasuhiro, Higashi, Yumi, Shimizu, Yutaka, Nakano, Takeshi, Ochi, Yusuke, Yamada, Hiroaki, Matsuura, Nobushi, Imamoto, Akihiro, Kawaguchi, Kazuaki, Tabata, Koji, Hoshino, Hiroaki, Hioka, Takeshi, Saigusa, Shigehito, Date, Hiroki, Unno, Masaki, Sato, Jumpei, Kamata, You, Shimizu, Takahiro, Sugahara, Akio, Shibuya, Taira, Okuyama, Atsushi, Yamada, Junji, Minamoto, Takatoshi, Chibvongodze, Hardwell, Ojima, Naoki, Sugawara, Hiroshi, Kano, Masahiro, Lee, Jang-Woo, Mizukoshi, Hiroyuki, Yamashita, Ryuji, Abe, Kensaku, Morozumi, Naohito, Yoon, In-Soo, Ariki, Takuya, Hak Yuh, Jong, Htoo, Khin, Kato, Yosuke, Oyama, Yoshihiro, Jason Li, Yen-Lung, Watanabe, Yoshihisa, Kouchi, Toshiyuki, Hosono, Koji

“…This article reports a 1-Tb 3-b/cell 3-D flash memory fabricated with CMOS direct bonded array (CBA) technology…”
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Computationally Efficient Surrogate-Assisted Design of Pyramidal-Shaped 3-D Reflectarray Antennas by Mahouti, Peyman, Belen, Mehmet A., Calik, Nurullah, Koziel, Slawomir

“…Reflectarrays (RAs) have been attracting considerable interest in recent years due to their appealing features, in particular, the possibility of realizing pencil-beam radiation patterns, as in the phased arrays…”
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3-D AND-Type Flash Memory Architecture With High-κ Gate Dielectric for High-Density Synaptic Devices by Seo, Young-Tak, Kwon, Dongseok, Noh, Yoohyun, Lee, Soochang, Park, Min-Kyu, Woo, Sung Yun, Park, Byung-Gook, Lee, Jong-Ho

“…Advanced 3-D synaptic devices with a stackable AND-type rounded dual channel (RDC) flash memory structure are proposed for neuromorphic networks…”
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