Výsledky vyhľadávania - (("Field Programming gate array") OR ("Field Programming game array"))*

  1. 1

    High Speed and Performance analysis of Multiplier in Field Programming Gate Array Autor Gowthami, M, Jalall S, Kehkeshan, Aby Varkey M, Tony, Kiruthika, K

    ISSN: 1757-8981, 1757-899X
    Vydavateľské údaje: Bristol IOP Publishing 01.03.2021
    “…This paper reads pipelined increase procedures for execution on FPGAs with accentuation on the usage of FPGA equipment asset. Execution of multiplier usage are…”
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  2. 2

    Implementation of Carrier-Based Simple Boost Pulse Width Modulation (PWM) for Z-Source Inverter (ZSI) using Field Programming Gate Array (FPGA) Autor Muhammad, M, Rasin, Z, Jidin, A

    ISSN: 1757-8981, 1757-899X
    Vydavateľské údaje: Bristol IOP Publishing 01.08.2017
    “…In recent years, the research on the Z-source inverter (ZSI) has received a wide acceptance due to its attractive solution for example in the renewable energy…”
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  3. 3

    An efficient reconfigurable code rate cooperative low-density parity check codes for gigabits wide code encoder/decoder operations Autor Venkatesh, Divyashree Yamadur, Mallikarjunaiah, Komala, Srikantaswamy, Mallikarjunaswamy

    ISSN: 2088-8708, 2722-2578
    Vydavateľské údaje: 01.12.2023
    “…In recent days, extensive digital communication process has been performed. Due to this phenomenon, a proper maintenance of authentication, communication…”
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  4. 4

    Design of CSD based bi-orthogonal wavelet filter bank for medical image retrieval Autor Samantaray, Aswini Kumar, Gorre, Pradeep, Sahoo, Prabodh Kumar

    ISSN: 2772-6711, 2772-6711
    Vydavateľské údaje: Elsevier Ltd 01.09.2023
    Vydané v e-Prime (01.09.2023)
    “…•In this work, design of a low-complex bi-orthogonal wavelet filter bank is proposed based on canonical signed digit (CSD) implementation.•The CSD technique…”
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  5. 5

    Fast Amplitude Estimation of Harmonics Using Undecimated Wavelet Packet Transform and Its Hardware Implementation Autor Tiwari, Vinay K., Umarikar, Amod C., Jain, Trapti

    ISSN: 0018-9456, 1557-9662
    Vydavateľské údaje: New York IEEE 01.01.2018
    “…Accurate and fast estimation of time-varying harmonics are essential requirements for online monitoring, analysis, and control of electrical power system. This…”
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  6. 6

    Hardware Implementation of Polyphase-Decomposition-Based Wavelet Filters for Power System Harmonics Estimation Autor Tiwari, Vinay K., Jain, Sachin K.

    ISSN: 0018-9456, 1557-9662
    Vydavateľské údaje: New York IEEE 01.07.2016
    “… and implement the proposed scheme on the Xilinx Artix-7 field-programming gate array AC701 board…”
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  7. 7

    10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform Autor Visconti, Paolo, Capoccia, Stefano, Venere, Eugenio, Velázquez, Ramiro, Fazio, Roberto de

    ISSN: 2079-9292, 2079-9292
    Vydavateľské údaje: Basel MDPI AG 01.10.2020
    Vydané v Electronics (Basel) (01.10.2020)
    “…The security of communication and computer systems is an increasingly important issue, nowadays pervading all areas of human activity (e.g., credit cards,…”
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  8. 8

    Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs Autor Brown, Grant, Gore, Ganesh, Gaillardon, Pierre-Emmanuel

    ISSN: 2159-3477
    Vydavateľské údaje: IEEE 20.06.2023
    “…Field Programmable Gate Arrays (FPGA) have grown in popularity in a myriad of applications due to their reconfigurablity and lower non-recurrent engineering…”
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  9. 9

    FPGA Eco Unit Commitment Based Gravitational Search Algorithm Integrating Plug-in Electric Vehicles Autor ElAzab, Heba-Allah I., Swief, R. A., Issa, Hanady H., El-Amary, Noha H., Balbaa, Alsnosy, Temraz, H. K.

    ISSN: 1996-1073, 1996-1073
    Vydavateľské údaje: Basel MDPI AG 01.10.2018
    Vydané v Energies (Basel) (01.10.2018)
    “…Smart grid architecture is one of the difficult constructions in electrical power systems. The main feature is divided into three layers; the first layer is…”
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  10. 10

    Towards IP integration on SoC: a case study of high-throughput and low-cost wrapper design on a novel IBUS architecture Autor Yang, Xiaokun, Sha, Shi, Unwala, Ishaq, Lu, Jiang

    ISSN: 1751-8601, 1751-861X, 2095-882X, 1751-861X, 2589-0514
    Vydavateľské údaje: Beijing The Institution of Engineering and Technology 01.11.2020
    “… in terms of field-programming gate array slice count, bus transfer latency, and energy consumption…”
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  11. 11

    Real-Time Controller Based on FPGA and DSP for Solar Ground Layer Adaptive Optics Prototype System at 1-m NVST Autor Kong, Lin, Zhu, Lei, Zhang, Lanqiang, Bao, Hua, Rao, Changhui

    ISSN: 1943-0655, 1943-0647
    Vydavateľské údaje: IEEE 01.04.2017
    Vydané v IEEE photonics journal (01.04.2017)
    “… A customized RTC based on a high-speed field programming gate array and a multi-core digital signal processor was developed for the solar GLAO prototype system at the 1-m New Vacuum Solar Telescope…”
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  12. 12

    Modeling and reliability analysis of three phase z-source AC-AC converter Autor Prasad, Hanuman, Maity, Tanmoy

    ISSN: 2300-2506, 1427-4221, 2300-2506
    Vydavateľské údaje: Warsaw De Gruyter Open 20.12.2017
    “…This paper presents the small signal modeling using the state space averaging technique and reliability analysis of a three-phase z-source ac-ac converter. By…”
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  13. 13

    FPGA-Based Motor Control Systems for Industrial Automation Autor Vaithianathan, Muthukumaran, Udkar, Shivakumar, Roy, Deepanjan, Reddy, Manjunath, Rajasekaran, Senkadir

    Vydavateľské údaje: IEEE 11.12.2024
    “…This study delineates the procedures for the development and execution of a motor control system for industrial automation that employs FPGAs. The objective is…”
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  14. 14

    High-Performance Computing with FPGA-Based Parallel Data Processing Systems Autor Vaithianathan, Muthukumaran, Udkar, Shivakumar, Roy, Deepanjan, Reddy, Manjunath, Rajasekaran, Senkadir

    Vydavateľské údaje: IEEE 11.12.2024
    “…Traditional architectures of Central Processing Units (CPUs) and Graphics Processing Units (GPUs) are becoming unsuitable for High-Performance Computing (HPC)…”
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  15. 15

    FPGA-Based Adaptive Beamforming System for Improved Wireless Communication Performance Autor Vaithianathan, Muthukumaran, Shunyee Frank, Ng, Patil, Mahesh, Reddy, Manjunath, Rajasekaran, Senkadir, Udaya Krishnan, M

    ISBN: 9798350374933
    Vydavateľské údaje: IEEE 06.09.2024
    “…The study describes an innovative adaptive beamforming system that improves wireless communication performance through the utilization of field-programmable…”
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  16. 16

    Video Encryption and Decryption System Implemented on FPGA for Secure Communication Autor Vaithianathan, Muthukumaran, Ng, Shunyee Frank, Patil, Mahesh, Reddy, Manjunath, Rajasekaran, Senkadir, Sakthekannan, M S

    ISBN: 9798350374933
    Vydavateľské údaje: IEEE 06.09.2024
    “…This research paper introduces an innovative method for ensuring the security of video communication by implementing a video encryption and decryption system…”
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  17. 17

    High-Entropy Metastable Jitter-Based True Random Number Generator (TRNG) Autor AKter, Sonia, Williams, Shelby, Kirtonia, Prosen, Khalil, Kasem, Bayoumi, Magdy

    ISSN: 2766-5186
    Vydavateľské údaje: IEEE 11.04.2025
    “…True Random Number Generator (TRNG) is a pivotal component of hardware-security modules in IoT devices. In this paper, we propose a miniaturized Dual Input…”
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  18. 18

    Numeric-Digit Identifier based on Convolutional Neural Networks on Field-Programmable Gate Array Autor VinothKumar, C, Kannan, N

    Vydavateľské údaje: IEEE 06.07.2023
    “…Convolutional Neural Networks (CNNs) are increasingly employed for voice recognition, image segmentation, and digit classification. Hardware support techniques…”
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  19. 19

    Design and FPGA Implementation of an Efficient Architecture for Noise Removal in ECG Signals Using Lifting-Based Wavelet Denoising Autor Gon, Anusaka, Mukherjee, Atin

    Vydavateľské údaje: IEEE 04.05.2023
    “…Noise removal is the most crucial pre-processing step for present-generation biomedical wearable electrocardiogram (ECG) patches and devices to provide…”
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  20. 20

    Realization of Human Eye Pupil Detection System using Canny Edge Detector and Circular Hough Transform Technique Autor M, Srikrishna, G, Nirmala

    Vydavateľské údaje: IEEE 04.05.2023
    “…Near Infrared (NIR) images involves the generation of an edge-map by combining two edge-maps generated from the same eye image for pupil detection. It is…”
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