Výsledky vyhľadávania - "variable-length coding/decoding"

Studies and advances on joint source-channel encoding/decoding techniques in flow media communications Autor Tu, GuoFang, Liu, JianJun, Zhang, Can, Gao, ShaoShuai, Li, ShiDong

“…Joint source-channel coding/decoding （JSCC/JSCD） techniques in flow media communications have become a state-of-the-art and one of the challenging research…”
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Japanese Inventors Develop Variable Length Coding, Decoding Method

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US Patent Issued to K.K. Kabushiki Kaisha Toshiba on Nov. 5 for "Apparatus for coding or decoding an image by executing variable-length coding/decoding and fixed-length coding/decoding" (Japanese Inventor)

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Patent No. 7,714,752 Issued on May 11, Assigned to Panasonic for Variable Length Coding, Decoding Method (Japanese Inventors)

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Patent No. RE40,909 Issued on Sept. 8, Assigned to Samsung Electronics for Variable-Length Coding, Decoding Methods (South Korean Inventors)

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Patent No. 7,646,318 Issued on Jan. 12, Assigned to Electronics and Telecommunications Research Institute for H.264 Context Adaptive Variable Length Coding Decoding Method (South Korean Inventors)

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Patent No. RE40,980 Issued on Nov. 17, Assigned to Samsung Electronics for Adaptive Variable-length Coding, Decoding Method (South Korean Inventors)

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Patent No. RE40,782 Issued on June 23, Assigned to Samsung Electronics for Adaptive Variable-Length Coding, Decoding Method (South Korean Inventors)

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Patent No. RE40,783 Issued on June 23, Assigned to Samsung Electronics for Adaptive Variable-Length Coding, Decoding Method (South Korean Inventors)

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Patent No. 7,539,346 Issued on May 26, Assigned to CS Technology for Fast Context Adaptive Variable Length Coding, Decoding Method (South Korean Inventor)

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A New Coeff-Token Decoding Method With Efficient Memory Access in H.264/AVC Video Coding Standard Autor Moon, Yong Ho

“…In general, a large amount of memory accesses are required for context-based adaptive variable-length coding decoding in H.264/AVC standard…”
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A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor Autor Mohri, A., Yamada, A., Yoshida, Y., Sato, H., Takata, H., Nakakimura, K., Hashizume, M., Shimotsuma, Y., Tsuchihashi, K.

“… The dedicated hardware for variable-length coding/decoding can encode and decode codes for both the DVCR and the MPEG-2 by changing translation tables…”
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A real-time digital VCR encode/decode and MPEG2 decode LSI implemented on a dual-issue RISC processor Autor Mohri, A., Yamada, A., Yoshida, T., Sato, H., Takata, H., Nakakimura, K., Tsuchihashi, K., Shimotsuma, Y.

“…) with dedicated hardware for variable length coding/decoding and video-block loading. The DRISC achieves 972MOPS and supports multiple standards with the block-level dedicated…”
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A video digital signal processor with a vector-pipeline architecture Autor Toyokura, M., Okamoto, K., Kodama, H., Ohtani, A., Araki, T., Aono, K.

“… The VDSP performs motion vector detection, motion compensation, DCT/IDCT, loop filtering, quantization/inverse quantization, and variable length coding/decoding specified in CCIT H.261…”
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