Výsledky vyhledávání - "parallel computing methodologies"
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SFLU: Synchronization-Free Sparse LU Factorization for Fast Circuit Simulation on GPUs
Vydáno: IEEE 05.12.2021Vydáno v 2021 58th ACM/IEEE Design Automation Conference (DAC) (05.12.2021)“…Sparse LU factorization is one of the key building blocks of sparse direct solvers and often dominates the computing time of circuit simulation programs…”
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Parallelizing Maximal Clique Enumeration on GPUs
Vydáno: IEEE 21.10.2023Vydáno v 2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT) (21.10.2023)“…We present a GPU solution for exact maximal clique enumeration (MCE) that performs a search tree traversal following the Bron-Kerbosch algorithm. Prior works…”
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TSUNAMI: A GPU Implementation of the WFA Algorithm
Vydáno: IEEE 21.10.2023Vydáno v 2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT) (21.10.2023)“…Pairwise sequence alignment represents a fundamental step in the genome assembly pipeline, being the most time-consuming step and the bottleneck factor in…”
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PID-Comm: A Fast and Flexible Collective Communication Framework for Commodity Processing-in-DIMM Devices
Vydáno: IEEE 29.06.2024Vydáno v 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) (29.06.2024)“…Recent dual in-line memory modules (DIMMs) are starting to support processing-in-memory (PIM) by associating their memory banks with processing elements (PEs),…”
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Versatile Cross-platform Compilation Toolchain for Schrödinger-style Quantum Circuit Simulation
Vydáno: IEEE 22.06.2025Vydáno v 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…While existing quantum hardware resources have limited availability and reliability, there is a growing demand for exploring and verifying quantum algorithms…”
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DARIS: An Oversubscribed Spatio-Temporal Scheduler for Real-Time DNN Inference on GPUs
Vydáno: IEEE 22.06.2025Vydáno v 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…The widespread use of Deep Neural Networks (DNNs) is limited by high computational demands, especially in constrained environments. GPUs, though effective…”
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Skywalker: Efficient Alias-Method-Based Graph Sampling and Random Walk on GPUs
Vydáno: IEEE 01.09.2021Vydáno v 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.09.2021)“…Graph sampling and random walk operations, capturing the structural properties of graphs, are playing an important role today as we cannot directly adopt…”
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MAD-Max Beyond Single-Node: Enabling Large Machine Learning Model Acceleration on Distributed Systems
Vydáno: IEEE 29.06.2024Vydáno v 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) (29.06.2024)“…Training and deploying large-scale machine learning models is time-consuming, requires significant distributed computing infrastructures, and incurs high…”
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Splitwise: Efficient Generative LLM Inference Using Phase Splitting
Vydáno: IEEE 29.06.2024Vydáno v 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) (29.06.2024)“…Generative large language model (LLM) applications are growing rapidly, leading to large-scale deployments of expensive and power-hungry GPUs. Our…”
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HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE Inference
Vydáno: IEEE 22.06.2025Vydáno v 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…The Mixture of Experts (MoE) architecture has demonstrated significant advantages as it enables to increase the model capacity without a proportional increase…”
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DenSparSA: A Balanced Systolic Array Approach for Dense and Sparse Matrix Multiplication
Vydáno: IEEE 22.06.2025Vydáno v 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…Numerous studies have proposed hardware architectures to accelerate sparse matrix multiplication, but these approaches often incur substantial area and power…”
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NDFT: Accelerating Density Functional Theory Calculations via Hardware/Software Co-Design on Near-Data Computing System
Vydáno: IEEE 22.06.2025Vydáno v 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…Linear-response time-dependent Density Functional Theory (LR-TDDFT) is a widely used method for accurately predicting the excited-state properties of physical…”
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OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration
Vydáno: IEEE 09.07.2023Vydáno v 2023 60th ACM/IEEE Design Automation Conference (DAC) (09.07.2023)“…Design rule checking (DRC) is an essential procedure in physical verification, yet few open-source DRC tools are accessible in academia. To fill in the gap, we…”
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Polygeist: Raising C to Polyhedral MLIR
Vydáno: IEEE 01.09.2021Vydáno v 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.09.2021)“…We present Polygeist, a new compilation flow that connects the MLIR compiler infrastructure to cutting edge polyhedral optimization tools. It consists of a C…”
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pSyncPIM: Partially Synchronous Execution of Sparse Matrix Operations for All-Bank PIM Architectures
Vydáno: IEEE 29.06.2024Vydáno v 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) (29.06.2024)“…Recent commercial incarnations of processing-in-memory (PIM) maintain the standard DRAM interface and employ the all-bank mode execution to maximize bank-level…”
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Scalpel: Customizing DNN pruning to the underlying hardware parallelism
Vydáno: ACM 01.06.2017Vydáno v 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA) (01.06.2017)“…As the size of Deep Neural Networks (DNNs) continues to grow to increase accuracy and solve more complex problems, their energy footprint also scales. Weight…”
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Leveraging Difference Recurrence Relations for High-Performance GPU Genome Alignment
Vydáno: ACM 13.10.2024Vydáno v 2024 33rd International Conference on Parallel Architectures and Compilation Techniques (PACT) (13.10.2024)“…Genome pairwise sequence alignment is one of the most computationally intensive workloads in many genomic pipelines, often accounting for over 90% of the…”
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Accelerating Fourier and Number Theoretic Transforms using Tensor Cores and Warp Shuffles
Vydáno: IEEE 01.09.2021Vydáno v 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.09.2021)“…The discrete Fourier transform (DFT) and its specialized case, the number theoretic transform (NTT), are two important mathematical tools having applications…”
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SimplePIM: A Software Framework for Productive and Efficient Processing-in-Memory
Vydáno: IEEE 21.10.2023Vydáno v 2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT) (21.10.2023)“…Data movement between memory and processors is a major bottleneck in modern computing systems. The processing-in-memory (PIM) paradigm aims to alleviate this…”
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Seer: Predictive Runtime Kernel Selection for Irregular Problems
ISSN: 2643-2838Vydáno: IEEE 02.03.2024Vydáno v Proceedings / International Symposium on Code Generation and Optimization (02.03.2024)“…Modern GPUs are designed for regular problems and suffer from load imbalance when processing irregular data. Prior to our work, a domain expert selects the…”
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