Search Results - "decoder implementation"
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Efficient Implementation of 400 Gbps Optical Communication FEC
ISSN: 1549-8328, 1558-0806Published: New York IEEE 01.01.2021Published in IEEE transactions on circuits and systems. I, Regular papers (01.01.2021)“…We focus on a hardware implementation of the concatenated forward error-correction (FEC) decoder defined in 400ZR implementation agreement to provide a…”
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Journal Article -
2
Capacity-approaching protograph codes
ISSN: 0733-8716, 1558-0008Published: New York IEEE 01.08.2009Published in IEEE journal on selected areas in communications (01.08.2009)“…This paper discusses construction of protograph-based low-density parity-check (LDPC) codes. Emphasis is placed on protograph ensembles whose typical minimum…”
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3
Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing
ISSN: 1939-8018, 1939-8115Published: New York Springer US 01.10.2022Published in Journal of signal processing systems (01.10.2022)“…This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new…”
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4
Implementation aspects of LDPC convolutional codes
ISSN: 0090-6778, 1558-0857, 1558-0857Published: New York, NY IEEE 01.07.2008Published in IEEE transactions on communications (01.07.2008)“…Potentially large storage requirements and long initial decoding delays are two practical issues related to the decoding of low-density parity-check (LDPC)…”
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5
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices
ISSN: 0090-6778, 1558-0857Published: New York, NY IEEE 01.11.2009Published in IEEE transactions on communications (01.11.2009)“…Many classes of high-performance low-density parity-check (LDPC) codes are based on parity check matrices composed of permutation submatrices. We describe the…”
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6
Non-binary LDPC Decoders Design for Maximizing Throughput of an FPGA Implementation
ISSN: 0278-081X, 1531-5878Published: New York Springer US 01.11.2016Published in Circuits, systems, and signal processing (01.11.2016)“…Most of the recently proposed hardware realizations for non-binary low-density parity-check decoders are ASIC oriented as they employ multiplierless…”
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7
Generic Description and Synthesis of LDPC Decoders
ISSN: 0090-6778, 1558-0857Published: New York, NY IEEE 01.11.2007Published in IEEE transactions on communications (01.11.2007)“…Through a rapid survey of the architecture of low-density parity-check (LDPC) decoders, this paper proposes a general framework to describe and compare the…”
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8
Pipeline processing in low-density parity-check codes hardware decoder
ISSN: 0239-7528, 2300-1917Published: Warsaw Versita 01.06.2011Published in Bulletin of the Polish Academy of Sciences. Technical sciences (01.06.2011)“…Low-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a…”
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9
Hardware-oriented turbo-product codes decoder architecture
Published: IEEE 01.09.2017Published in IDAACS 2017 : proceedings of the 2017 IEEE 9th International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications : September 21-23, 2017, Bucharest, Romania (01.09.2017)“…Model of Turbo-Product Codes decoder architecture and method for construction of Turbo-Product Codes decoder are proposed in the paper. The model describes…”
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Conference Proceeding -
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Simplified check node processing in nonbinary LDPC decoders
ISBN: 1424467446, 9781424467440ISSN: 2165-4700Published: IEEE 01.09.2010Published in 2010 6th International Symposium on Turbo Codes & Iterative Information Processing (01.09.2010)“…This paper deals with low-complexity algorithms for the check node processing in nonbinary LDPC decoders. After a review of the state-of-the-art, we focus on…”
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Conference Proceeding -
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A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders
ISBN: 146732986X, 9781467329866ISSN: 2162-3562Published: IEEE 01.10.2012Published in 2012 IEEE Workshop on Signal Processing Systems (01.10.2012)“…Parallel turbo decoding techniques to achieve high throughput have been extensively investigated in the literature. These techniques are commonly combined. In…”
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Conference Proceeding -
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Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"
ISSN: 0018-9340Published: IEEE 01.03.1979Published in IEEE transactions on computers (01.03.1979)“…An efficient, optimal test sequence for detecting multiple stuck-at faults in random access memories (RAM's) for any decoder implementation is presented…”
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13
Partial Order-Based Decoding of Rate-1 Nodes in Fast Simplified Successive-Cancellation List Decoders for Polar Codes
ISSN: 2079-9292, 2079-9292Published: Basel MDPI AG 01.02.2022Published in Electronics (Basel) (01.02.2022)“…Polar codes are the first family of error-correcting codes that can achieve channel capacity. Among the known decoding algorithms, Successive-Cancellation List…”
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Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms
ISSN: 1522-4880Published: IEEE 01.10.2014Published in Proceedings - International Conference on Image Processing (01.10.2014)“…MPEG High Efficient Video Coding (HEVC) is likely to emerge as the video coding standard for HD and Ultra-HD TV resolutions. The two elements that push HEVC…”
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