Search Results - "Software and its engineering Software notations and tools Compilers"
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HexT5: Unified Pre-Training for Stripped Binary Code Information Inference
ISSN: 2643-1572Published: IEEE 11.09.2023Published in IEEE/ACM International Conference on Automated Software Engineering : [proceedings] (11.09.2023)“…Decompilation is a widely used process for reverse engineers to significantly enhance code readability by lifting assembly code to a higher-level C-like…”
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Speculative Decoding for Verilog: Speed and Quality, All in One
Published: IEEE 22.06.2025Published in 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…The rapid advancement of large language models (LLMs) has revolutionized code generation tasks across various programming languages. However, the unique…”
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3
Whose Baseline Compiler is it Anyway?
ISSN: 2643-2838Published: IEEE 02.03.2024Published in Proceedings / International Symposium on Code Generation and Optimization (02.03.2024)“…Compilers face an intrinsic tradeoff between compilation speed and code quality. The tradeoff is particularly stark in a dynamic setting where JIT compilation…”
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4
Experiences Building an MLIR-Based SYCL Compiler
ISSN: 2643-2838Published: IEEE 02.03.2024Published in Proceedings / International Symposium on Code Generation and Optimization (02.03.2024)“…Similar to other programming models, compilers for SYCL, the open programming model for heterogeneous computing based on C++, would benefit from access to…”
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mlirSynth: Automatic, Retargetable Program Raising in Multi-Level IR Using Program Synthesis
Published: IEEE 21.10.2023Published in 2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT) (21.10.2023)“…MLIR is an emerging compiler infrastructure for modern hardware, but existing programs cannot take advantage of MLIR's high-performance compilation if they are…”
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6
A System-Level Dynamic Binary Translator Using Automatically-Learned Translation Rules
ISSN: 2643-2838Published: IEEE 02.03.2024Published in Proceedings / International Symposium on Code Generation and Optimization (02.03.2024)“…System-level emulators have been used extensively for the design, debugging and evaluation of the system software. They work by providing a system-level…”
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7
A Flexible Approach to Autotuning Multi-Pass Machine Learning Compilers
Published: IEEE 01.09.2021Published in 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.09.2021)“…Search-based techniques have been demonstrated effective in solving complex optimization problems that arise in domain-specific compilers for machine learning…”
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8
Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs
Published: IEEE 22.06.2025Published in 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…To fully harness emerging computing architectures, compilers must provide intuitive input handling alongside powerful code optimization to unlock maximum…”
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Polygeist: Raising C to Polyhedral MLIR
Published: IEEE 01.09.2021Published in 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.09.2021)“…We present Polygeist, a new compilation flow that connects the MLIR compiler infrastructure to cutting edge polyhedral optimization tools. It consists of a C…”
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10
oneDNN Graph Compiler: A Hybrid Approach for High-Performance Deep Learning Compilation
ISSN: 2643-2838Published: IEEE 02.03.2024Published in Proceedings / International Symposium on Code Generation and Optimization (02.03.2024)“…With the rapid development of deep learning models and hardware support for dense computing, the deep learning (DL) workload characteristics changed…”
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11
Representing Data Collections in an SSA Form
ISSN: 2643-2838Published: IEEE 02.03.2024Published in Proceedings / International Symposium on Code Generation and Optimization (02.03.2024)“…Compiler research and development has treated computation as the primary driver of performance improvements in C/C++ programs, leaving memory optimizations as…”
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12
Bridging Gaps in LLM Code Translation: Reducing Errors with Call Graphs and Bridged Debuggers
ISSN: 2643-1572Published: ACM 27.10.2024Published in IEEE/ACM International Conference on Automated Software Engineering : [proceedings] (27.10.2024)“…When using large language models (LLMs) for code translation of complex software, numerous compilation and runtime errors can occur due to insufficient context…”
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13
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Published: IEEE 22.06.2025Published in 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…Recently, there has been a growing interest in leveraging Large Language Models for Verilog code generation. However, the current quality of the generated…”
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14
Compiler Auto-Tuning via Critical Flag Selection
ISSN: 2643-1572Published: IEEE 11.09.2023Published in IEEE/ACM International Conference on Automated Software Engineering : [proceedings] (11.09.2023)“…Widely used compilers like GCC usually have hundreds of optimizations controlled by optimization flags, which can be enabled or disabled during compilation to…”
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15
Toast: A Heterogeneous Memory Management System
Published: ACM 13.10.2024Published in 2024 33rd International Conference on Parallel Architectures and Compilation Techniques (PACT) (13.10.2024)“…Modern applications employ several heterogeneous memory types for improved performance, security, and reliability. To manage them, programmers must currently…”
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16
PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators
Published: IEEE 09.07.2023Published in 2023 60th ACM/IEEE Design Automation Conference (DAC) (09.07.2023)“…Crossbar-based PIM DNN accelerators can provide massively parallel in-situ operations. A specifically designed compiler is important to achieve high…”
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17
Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs
Published: IEEE 09.07.2023Published in 2023 60th ACM/IEEE Design Automation Conference (DAC) (09.07.2023)“…Digital signal processors (DSPs) commonly adopt VLIW-SIMD architecture and are extensively applied in most compute-heavy embedded sensing applications. The…”
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18
PolyTOPS: Reconfigurable and Flexible Polyhedral Scheduler
ISSN: 2643-2838Published: IEEE 02.03.2024Published in Proceedings / International Symposium on Code Generation and Optimization (02.03.2024)“…Polyhedral techniques have been widely used for automatic code optimization in low-level compilers and higher-level processes. Loop optimization is central to…”
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19
An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Published: IEEE 22.06.2025Published in 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…Sparsity is widely prevalent in real-world applications, yet existing compiler optimizations and code generation techniques for sparse computations remain…”
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20
Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
Published: IEEE 22.06.2025Published in 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…Coarse-Grained Reconfigurable Arrays (CGRAs) balance the performance and power efficiency in computing systems. Effective compilers play a crucial role in…”
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