Search Results - "Process Management- Multiprocessing/Multiprogramming"

nvshare: Practical GPU Sharing Without Memory Size Constraints by Alexopoulos, Georgios, Mitropoulos, Dimitris

“…GPUs are essential for accelerating Machine Learning (ML) work-loads. A common practice is deploying ML jobs as containers managed by an orchestrator such as…”
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VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing by Falahati, Hajar, Mahani, Negin, Cristal, Adrian, Unsal, Osman

“…Graphics Processing Units (GPUs) play a pivotal role in high-performance computing by utilizing the massive parallelism of concurrent thread execution to…”
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A Universal Method for Task Allocation on FP-FPS Multiprocessor Systems with Spin Locks by Zhao, Shuai, Chen, Nan, Fang, Yinjie, Li, Zhao, Chang, Wanli

“…Many complex real-time systems, such as increasingly automated vehicles and 5G wireless base stations, contain a large amount of shared resources that must be…”
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SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers by Yunqi Zhang, Laurenzano, Michael A., Mars, Jason, Lingjia Tang

“…One of the key challenges for improving efficiency in warehouse scale computers (WSCs) is to improve server utilization while guaranteeing the quality of…”
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Analysis and approximation of optimal co-scheduling on Chip Multiprocessors by Jiang, Yunlian, Shen, Xipeng, Jie, Chen, Tripathi, Rahul

“…Cache sharing among processors is important for Chip Multiprocessors to reduce inter-thread latency, but also brings cache contention, degrading program…”
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Automatic Thread Extraction with Decoupled Software Pipelining by Ottoni, Guilherme, Rangan, Ram, Stoler, Adam, August, David I.

“…Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing…”
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Rinnegan: Efficient resource use in heterogeneous architectures by Panneerselvam, Sankaralingam, Swift, Michael

“…Current processors provide a variety of different processing units to improve performance and power efficiency. For example, ARM's big.LITTLE, AMD's APUs, and…”
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Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime scheduling by Caheny, Paul, Casas, Marc, Moreto, Miquel, Gloaguen, Herve, Saintes, Maxime, Ayguade, Eduard, Labarta, Jesus, Valero, Mateo

“…Cache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the…”
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Scalability-based manycore partitioning by Sasaki, Hiroshi, Tanimoto, Teruo, Inoue, Koji, Nakamura, Hiroshi

“…Multicore processors have been popular for years, and the industry is gradually shifting towards the era of manycore processors. Single-thread performance of…”
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Online scalability characterization of data-parallel programs on many cores by Younghyun Cho, Oh, Surim, Egger, Bernhard

“…We present an accurate online scalability prediction model for data-parallel programs on NUMA many-core systems. Memory contention is considered to be the…”
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Energy efficient task scheduling on a multi-core platform using real-time energy measurements by Singh, Digvijay, Kaiser, William J.

“…This paper presents a large advance in energy-efficient operating system multiprocessor task scheduling with experimentally proven benefits for standard Linux…”
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A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms by Kempf, Torsten, Doerper, Malte, Leupers, R., Ascheid, G., Meyr, H., Kogel, Tim, Vanthournout, Bart

“…Heterogeneous Multi-Processor SoC platforms bear the potential to optimize conflicting performance, flexibility and energy efficiency constraints as imposed by…”
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Fairness and Throughput in Switch on Event Multithreading by Gabor, Ron, Weiss, Shlomo, Mendelson, Avi

“…The need to reduce power and complexity will increase the interest in Switch on Event multithreading (coarse grained multithreading). Switch On Event…”
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Spread-n-Share: Improving Application Performance and Cluster Throughput with Resource-aware Job Placement by Tang, Xiongchao, Wang, Haojie, Ma, Xiaosong, El-Sayed, Nosayba, Zhai, Jidong, Chen, Wenguang, Aboulnaga, Ashraf

“…Traditional batch job schedulers adopt the Compact-n-Exclusive (CE) strategy, packing processes of a parallel job into as few com-pute nodes as possible. While…”
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Multitasking workload scheduling on flexible-core chip multiprocessors by Gulati, Divya P., Kim, Changkyu, Sethumadhavan, Simha, Keckler, Stephen W., Burger, Doug

“…While technology trends have ushered in the age of chip multiprocessors (CMP), a fundamental question is what size to make each core. Most current commercial…”
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Continuous Path and Edge Profiling by Bond, Michael D., McKinley, Kathryn S.

“…Microarchitectures increasingly rely on dynamic optimization to improve performance in ways that are dif- ficult or impossible for ahead-of-time compilers…”
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Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities by Ohsawa, Taku, Takagi, Masamichi, Kawahara, Shoji, Matsushita, Satoshi

“…We propose a speculative multi-threading processor architecture called Pinot. Pinot exploits parallelism over a wide range of granularities without modifying…”
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RTOS Modeling for System Level Design by Gerstlauer, Andreas, Yu, Haobo, Gajski, Daniel D.

“…System level synthesis is widely seen as the solution for closing the productivity gap in system design. High level system models are used in system level…”
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Low Cost Task Migration Initiation in a Heterogeneous MP-SoC by Nollet, V., Avasare, P., Mignolet, J-Y., Verkest, D.

“…Run-time task migration in a heterogeneous multiprocessor System-on-Chip (MP-SoC) is a challenge that requires cooperation between the task and the operating…”
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Scheduling Hard-Real-Time Tasks with Backup Phasing Delay by Bertossi, Alan A., Mancini, Luigi V., Menapace, Alessandra

“…This paper presents several fault-tolerant extensions of the Rate-Monotonic First-Fit multiprocessor scheduling algorithm handling both active and passive task…”
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