Suchergebnisse - "Proceedings of the IEEE/ACM International Conference on Computer-Aided Design"

SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs von Sugiyama, Yuichi, Matsuo, Reoma, Shioya, Ryota

“… Various verification methods have been proposed for bug detection in central processing unit (CPU) designs, yet their effectiveness remains insufficient. We …”
Volltext

Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs von Wu, Yannan Nellie, Emer, Joel S., Sze, Vivienne

“… With Moore's law slowing down and Dennard scaling ended, energy-efficient domain-specific accelerators, such as deep neural network (DNN) processors for …”
Volltext

GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models von Fu, Yonggan, Zhang, Yongan, Yu, Zhongzhi, Li, Sixu, Ye, Zhifan, Li, Chaojian, Wan, Cheng, Lin, Yingyan Celine

“… The remarkable capabilities and intricate nature of Artificial Intelligence (AI) have dramatically escalated the imperative for specialized AI accelerators …”
Volltext

Optimal Layout Synthesis for Quantum Computing von Tan, Bochen, Cong, Jason

“… Recent years have witnessed the fast development of quantum computing. Researchers around the world are eager to run larger and larger quantum algorithms that …”
Volltext

MAGNet: A Modular Accelerator Generator for Neural Networks von Venkatesan, Rangharajan, Shao, Yakun Sophia, Wang, Miaorong, Clemons, Jason, Dai, Steve, Fojtik, Matthew, Keller, Ben, Klinefelter, Alicia, Pinckney, Nathaniel, Raina, Priyanka, Zhang, Yanqing, Zimmer, Brian, Dally, William J., Emer, Joel, Keckler, Stephen W., Khailany, Brucek

“… Deep neural networks have been adopted in a wide range of application domains, leading to high demand for inference accelerators. However, the high cost …”
Volltext

GAMMA: Automating the HW Mapping of DNN Models on Accelerators via Genetic Algorithm von Kao, Sheng-Chun, Krishna, Tushar

“… DNN layers are multi-dimensional loops that can be ordered, tiled, and scheduled in myriad ways across space and time on DNN accelerators. Each of these …”
Volltext

ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration von Yang, Xiaoxuan, Yan, Bonan, Li, Hai, Chen, Yiran

“… Transformer has emerged as a popular deep neural network (DNN) model for Neural Language Processing (NLP) applications and demonstrated excellent performance …”
Volltext

Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks von Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong

“… With the recent advancement of multilayer convolutional neural networks (CNN), deep learning has achieved amazing success in many areas, especially in visual …”
Volltext

Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation von Liu, Mingjie, Pinckney, Nathaniel, Khailany, Brucek, Ren, Haoxing

“… The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains. This paper proposes a benchmarking …”
Volltext

DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator von Zhang, Xiaofan, Ye, Hanchen, Wang, Junsong, Lin, Yonghua, Xiong, Jinjun, Hwu, Wen-Mei, Chen, Deming

“… Existing FPGA-based DNN accelerators typically fall into two design paradigms. Either they adopt a generic reusable architecture to support different DNN …”
Volltext

How to Efficiently Handle Complex Values? Implementing Decision Diagrams for Quantum Computing von Zulehner, Alwin, Hillmich, Stefan, Wille, Robert

“… Quantum computing promises substantial speedups by exploiting quantum mechanical phenomena such as superposition and entanglement. Corresponding design methods …”
Volltext

Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks von Ustun, Ecenur, Deng, Chenhui, Pal, Debjit, Li, Zhijing, Zhang, Zhiru

“… Modern heterogeneous FPGA architectures incorporate a variety of hardened blocks for boosting the performance of arithmetic-intensive designs, such as DSP …”
Volltext

VLSI Placement Parameter Optimization using Deep Reinforcement Learning von Agnesina, Anthony, Chang, Kyungwook, Lim, Sung Kyu

“… The quality of placement is essential in the physical design flow. To achieve PPA goals, a human engineer typically spends a considerable amount of time tuning …”
Volltext

Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks von Xie, Xi, Peng, Hongwu, Hasan, Amit, Huang, Shaoyi, Zhao, Jiahui, Fang, Haowen, Zhang, Wei, Geng, Tong, Khan, Omer, Ding, Caiwen

“… Graph Convolutional Networks (GCNs) are pivotal in extracting latent information from graph data across various domains, yet their acceleration on mainstream …”
Volltext

DeepGate2: Functionality-Aware Circuit Representation Learning von Shi, Zhengyuan, Pan, Hongyang, Khan, Sadaf, Li, Min, Liu, Yi, Huang, Junhua, Zhen, Hui-Ling, Yuan, Mingxuan, Chu, Zhufei, Xu, Qiang

“… Circuit representation learning aims to obtain neural repre-sentations of circuit elements and has emerged as a promising research direction that can be …”
Volltext

Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning von Gong, Chengyue, Jiang, Zixuan, Wang, Dilin, Lin, Yibo, Liu, Qiang, Pan, David Z.

“… Large scale deep neural networks (DNNs) have achieved remarkable successes in various artificial intelligence applications. However, high computational …”
Volltext

ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining von Mrazek, Vojtech, Vasicek, Zdenek, Sekanina, Lukas, Hanif, Muhammad Abdullah, Shafique, Muhammad

“… The state-of-the-art approaches employ approximate computing to reduce the energy consumption of DNN hardware. Approximate DNNs then require extensive …”
Volltext

BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks von Hakhamaneshi, Kourosh, Werblun, Nick, Abbeel, Pieter, Stojanovic, Vladimir

“… The discrepancy between post-layout and schematic simulation results continues to widen in analog design due in part to the domination of layout parasitics …”
Volltext

Robust GNN-Based Representation Learning for HLS von Sohrabizadeh, Atefeh, Bai, Yunsheng, Sun, Yizhou, Cong, Jason

“… The efficient and timely optimization of microarchitecture for a target application is hindered by the long evaluation runtime of a design candidate, creating …”
Volltext

Accelerating Framework of Transformer by Hardware Design and Model Compression Co-Optimization von Qi, Panjie, Sha, Edwin Hsing-Mean, Zhuge, Qingfeng, Peng, Hongwu, Huang, Shaoyi, Kong, Zhenglun, Song, Yuhong, Li, Bingbing

“… State-of-the-art Transformer-based models, with gigantic parameters, are difficult to be accommodated on resource constrained embedded devices. Moreover, with …”
Volltext