Výsledky vyhľadávania - "Proceedings of the Conference on Design, Automation and Test in Europe"

Top-Down System Level Design Methodology Using SpecC, VCC and SystemC Autor Cai, L., Gajski, D., Kritzinger, P., Olivares, M.

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Speeding up SAT for EDA Autor Pilarski, S., Hu, G.

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HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model Autor Vazquez, P., Juan-Chico, J., Bellido, M., Acosta, A., Valencia, M.

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Modelling SoC devices for virtual test using VHDL Autor Rona, M., Krampl, G.

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Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices Autor Krishnaswamy, Smita, Viamontes, George F., Markov, Igor L., Hayes, John P.

“…Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational…”
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A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip Autor Bjerregaard, Tobias, Sparso, Jens

“…On-chip networks for future system-on-chip designs need simple, high performance implementations. In order to promote system-level integrity, guaranteed…”
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On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs Autor Kastensmidt, F. Lima, Sterpone, L., Carro, L., Reorda, M. Sonza

“…Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in…”
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Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives Autor Bougard, Bruno, Catthoor, Francky, Daly, Denis C., Chandrakasan, Anantha, Dehaene, Wim

“…Wireless microsensor networks, which have been the topic of intensive research in recent years, are now emerging in industrial applications. An important…”
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A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification Autor Goossens, Kees, Dielissen, John, Gangwal, Om Prakash, Pestana, Santiago Gonzalez, Radulescu, Andrei, Rijpkema, Edwin

“…Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for…”
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Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach Autor Yang, Shengqi, Wolf, Wayne, Vijaykrishnan, N., Serpanos, D. N., Xie, Yuan

“…A novel power attack resistant cryptosystem is presented in this paper. Security in digital computing and communication is becoming increasingly important…”
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Quantum Circuit Simplification Using Templates Autor Maslov, D., Young, C., Miller, D. M., Dueck, G. W.

“…Optimal synthesis of quantum circuits is intractable and heuristic methods must be employed. Templates are a general approach to reversible and quantum circuit…”
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Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring Autor Arora, Divya, Ravi, Srivaths, Raghunathan, Anand, Jha, Niraj K.

“…Security is emerging as an important concern in embedded system design. The security of embedded systems is often compromised due to vulnerabilities in…”
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Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications Autor Zhang, Lintao, Malik, Sharad

“…As the use of SAT solvers as core engines in EDA applications grows, it becomes increasingly important to validate their correctness. In this paper, we…”
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An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor Autor Yang, Chuan-Yue, Chen, Jian-Jia, Kuo, Tei-Wei

“…In the recent decade, voltage scaling has become an attractive feature for many system component designs. In this paper, we consider energy-efficient real-time…”
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A Complete Network-On-Chip Emulation Framework Autor Genko, N., Atienza, D., Micheli, G. De, Mendias, J. M., Hermida, R., Catthoor, F.

“…Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing…”
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Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits Autor Dhillon, Yuvraj Singh, Diril, Abdulkadir Utku, Chatterjee, Abhijit

“…Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node…”
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Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems Autor Izosimov, Viacheslav, Pop, Paul, Eles, Petru, Peng, Zebo

“…In this paper we present an approach to the design optimization of fault-tolerant embedded systems for safety-critical applications.Processes are statically…”
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A Synthesizable IP Core for DVB-S2 LDPC Code Decoding Autor Kienle, Frank, Brack, Torben, Wehn, Norbert

“…The new standard for digital video broadcast DVB-S2 features Low-Density Parity-Check (LDPC) codes as their channel coding scheme. The codes are defined for…”
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A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms Autor Kempf, Torsten, Doerper, Malte, Leupers, R., Ascheid, G., Meyr, H., Kogel, Tim, Vanthournout, Bart

“…Heterogeneous Multi-Processor SoC platforms bear the potential to optimize conflicting performance, flexibility and energy efficiency constraints as imposed by…”
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A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs Autor Tiri, Kris, Verbauwhede, Ingrid

“…This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal…”
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