Suchergebnisse - "Proceedings of the ASP-DAC ... Asia and South Pacific Design Automation Conference"

RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model von Lu, Yao, Liu, Shang, Zhang, Qijun, Xie, Zhiyao

“… Inspired by the recent success of large language models (LLMs) like ChatGPT, researchers start to explore the adoption of LLMs for agile hardware design, such …”
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DRiLLS: Deep Reinforcement Learning for Logic Synthesis von Hosny, Abdelrahman, Hashemi, Soheil, Shalan, Mohamed, Reda, Sherief

“… Logic synthesis requires extensive tuning of the synthesis optimization flow where the quality of results (QoR) depends on the sequence of optimizations used …”
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Design space exploration of FPGA-based Deep Convolutional Neural Networks von Motamedi, Mohammad, Gysel, Philipp, Akella, Venkatesh, Ghiasi, Soheil

“… Deep Convolutional Neural Networks (DCNN) have proven to be very effective in many pattern recognition applications, such as image classification and speech …”
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Security analysis on consumer and industrial IoT devices von Wurm, Jacob, Khoa Hoang, Arias, Orlando, Sadeghi, Ahmad-Reza, Jin, Yier

“… The fast development of Internet of Things (IoT) and cyber-physical systems (CPS) has triggered a large demand of smart devices which are loaded with sensors …”
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Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits von Wille, Robert, Keszocze, Oliver, Walter, Marcel, Rohrs, Patrick, Chattopadhyay, Anupam, Drechsler, Rolf

“… Ensuring nearest neighbor compliance of quantum circuits by inserting SWAP gates has heavily been considered in the past. Here, quantum gates are considered …”
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Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications von Matsubara, Satoshi, Takatsu, Motomu, Miyazawa, Toshiyuki, Shibasaki, Takayuki, Watanabe, Yasuhiro, Takemoto, Kazuya, Tamura, Hirotaka

“… A Digital Annealer (DA) is a dedicated architecture for high-speed solving of combinatorial optimization problems mapped to an Ising model. With fully coupled …”
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PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network von Xie, Zhiyao, Ren, Haoxing, Khailany, Brucek, Sheng, Ye, Santosh, Santosh, Hu, Jiang, Chen, Yiran

“… IR drop is a fundamental constraint required by almost all chip designs. However, its evaluation usually takes a long time that hinders mitigation techniques …”
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MINT: Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks von Yin, Ruokai, Li, Yuhang, Moitra, Abhishek, Panda, Priyadarshini

“… We propose Multiplier-less INTeger (MINT) quantization, a uniform quantization scheme that efficiently compresses weights and membrane potentials in spiking …”
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Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture von Gu, Jiaqi, Zhao, Zheng, Feng, Chenghao, Liu, Mingjie, Chen, Ray T., Pan, David Z.

“… As a promising neuromorphic framework, the optical neural network (ONN) demonstrates ultra-high inference speed with low energy consumption. However, the …”
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Invited Paper: Software/Hardware Co-design for LLM and Its Application for Design Verification von Wan, Lily Jiaxin, Huang, Yingbing, Li, Yuhong, Ye, Hanchen, Wang, Jinghua, Zhang, Xiaofan, Chen, Deming

“… The widespread adoption of Large Language Models (LLMs) is impeded by their demanding compute and memory resources. The first task of this paper is to explore …”
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TENET: Temporal CNN with Attention for Anomaly Detection in Automotive Cyber-Physical Systems von Thiruloga, Sooryaa Vignesh, Kukkala, Vipin Kumar, Pasricha, Sudeep

“… Modern vehicles have multiple electronic control units (ECUs) that are connected together as part of a complex distributed cyber-physical system (CPS). The …”
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Using Boolean Satisfiability for Exact Shuttling in Trapped-Ion Quantum Computers von Schoenberger, Daniel, Hillmich, Stefan, Brandl, Matthias, Wille, Robert

“… Trapped ions are a promising technology for building scalable quantum computers. Not only can they provide a high qubit quality, but they also enable modular …”
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When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies von Yan, Zheyu, Shi, Yiyu, Liao, Wang, Hashimoto, Masanori, Zhou, Xichuan, Zhuo, Cheng

“… Deep Neural Network has proved its potential in various perception tasks and hence become an appealing option for interpretation and data processing in …”
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The Need for Speed: Efficient Exact Simulation of Silicon Dangling Bond Logic von Drewniok, Jan, Walter, Marcel, Wille, Robert

“… The Silicon Dangling Bond (SiDB) logic platform, an emerging computational beyond-CMOS nanotechnology, is a promising competitor due to its ability to achieve …”
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Tiny but Accurate: A Pruned, Quantized and Optimized Memristor Crossbar Framework for Ultra Efficient DNN Implementation von Ma, Xiaolong, Yuan, Geng, Lin, Sheng, Ding, Caiwen, Yu, Fuxun, Liu, Tao, Wen, Wujie, Chen, Xiang, Wang, Yanzhi

“… The memristor crossbar array has emerged as an intrinsically suitable matrix computation and low-power acceleration framework for DNN applications. Many …”
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Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis von Riener, Heinz, Lee, Siang-Yun, Mishchenko, Alan, De Micheli, Giovanni

“… The paper presents a novel DAG-aware Boolean rewriting algorithm for restructuring combinational logic before technology mapping. The algorithm, called window …”
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FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning von Xie, Zhiyao, Fang, Guan-Qi, Huang, Yu-Hung, Ren, Haoxing, Zhang, Yanqing, Khailany, Brucek, Fang, Shao-Yun, Hu, Jiang, Chen, Yiran, Barboza, Erick Carvajal

“… Design flow parameters are of utmost importance to chip design quality and require a painfully long time to evaluate their effects. In reality, flow parameter …”
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SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design von Chen, Shixin, Zheng, Su, Bai, Chen, Zhao, Wenqian, Yin, Shuo, Bai, Yang, Yu, Bei

“… Designing a system-on-chip (SoC) for deep neural network (DNN) acceleration requires balancing multiple metrics such as latency, power, and area. However, most …”
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Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets von Yang, Zhuoping, Ji, Shixin, Chen, Xingzhen, Zhuang, Jinming, Zhang, Weifeng, Jani, Dharmesh, Zhou, Peipei

“… Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever-increasing computing demands in today's data …”
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Qubit placement to minimize communication overhead in 2D quantum architectures von Shafaei, Alireza, Saeedi, Mehdi, Pedram, Massoud

“… Regular, local-neighbor topologies of quantum architectures restrict interactions to adjacent qubits, which in turn increases the latency of quantum circuits …”
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