Výsledky vyhledávání - "Proceedings International Conference on Computer Design VLSI in Computers and Processors"

Current-based testing for analog and mixed-signal circuits Autor Velasco-Medina, J., Nicolaidis, M.

“…A new test technique for analog and mixed-signal circuits which employs current signals as input test stimuli is presented in this paper. With the…”
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A new non-restoring square root algorithm and its VLSI implementations Autor Yamin Li, Wanming Chu

“…We present a new non-restoring square root algorithm that is very efficient to implement. The new algorithm presented here has the following features unlike…”
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TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model Autor Takamura, A., Kuwako, M., Imai, M., Fujii, T., Ozawa, M., Fukasaku, I., Ueno, Y., Nanya, T.

“…Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current…”
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Software power estimation and optimization for high performance, 32-bit embedded processors Autor Russell, J.T., Jacome, M.F.

“…A software energy estimation model is presented for a family of high performance, integrated, 32-bit embedded RISC processors. This model is significantly less…”
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The Alpha 21264 microprocessor architecture Autor Kessler, R.E., McLellan, E.J., Webb, D.A.

“…The 21264 is the third generation Alpha microprocessor from Compaq Computer (formerly Digital Equipment) Corporation. This microprocessor achieves the…”
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Vector restoration based static compaction of test sequences for synchronous sequential circuits Autor Pomeranz, I., Reddy, S.M.

“…The authors propose a new procedure for static compaction that belongs to the class of procedures that omit test vectors from a given test sequence in order to…”
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Low power SRAM design using hierarchical divided bit-line approach Autor Karandikar, A., Parhi, K.K.

“…This paper presents a novel hierarchical divided bit-line approach for reducing active power in SRAMs by reducing bit-line capacitance. Two or more 6T SRAM…”
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Properties of the input pattern fault model Autor Blanton, R.D., Hayes, J.P.

“…Recent work in IC failure analysis strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern…”
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Circuit design techniques for a gigahertz integer microprocessor Autor Nowka, K.J., Galambos, T.

“…Using highly optimized, custom circuits and fast dynamic array control structures, a small team of designers at the IBM Austin Research Laboratory has…”
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CMOS gate delay models for general RLC loading Autor Arunachalam, R., Dartu, F., Pileggi, L.T.

“…Gate and cell level timing analysis remains popular yet inherently incompatible with RC and RCL interconnect loads. The Ceff concept was proposed in Qian et…”
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Accuracy sensitive word-length selection for algorithm optimization Autor Wadekar, S.A., Parker, A.C.

“…In typical hardware implementations of an arithmetic-intensive algorithm, designers must determine the word lengths of resources such as adders, multipliers,…”
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Reducing state loss for effective trace sampling of superscalar processors Autor Conte, T.M., Hirsch, M.A., Menezes, K.N.

“…There is a wealth of technological alternatives that can be incorporated into a processor design. These include reservation station designs, functional unit…”
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Power constrained design of multiprocessor interconnection networks Autor Patel, C.S., Chai, S.M., Yalamanchili, S., Schimmel, D.E.

“…The paper considers the power constrained design of orthogonal multiprocessor interconnection networks. The authors present a detailed model of message latency…”
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Asynchronous wrapper for heterogeneous systems Autor Bormann, D.S., Cheung, P.Y.K.

“…We propose a new method for creating globally asynchronous locally synchronous (GALS) circuits. Each locally synchronous module is surrounded by an…”
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Pausible clocking: a first step toward heterogeneous systems Autor Yun, K.Y., Donohue, R.P.

“…This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating…”
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Circular buffered switch design with wormhole routing and virtual channels Autor Ni, N., Pirvu, M., Bhuyan, L.

“…Switch design for interconnection networks plays an important role in the overall performance of multiprocessors and computer networks. In this paper, a new…”
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Adaptive synchronization Autor Ginosar, R., Kol, R.

“…Delay variations are typically accounted for by increasing cycle time margins. Adaptive synchronization eliminates this on inter-modular interfaces in very…”
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The ARM9 family-high performance microprocessors for embedded applications Autor Segars, S.

“…Portable applications such as mobile phones, pagers, and PDAs are continually growing in sophistication. This places an increasing burden on the embedded…”
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Clustering and load balancing for buffered clock tree synthesis Autor Mehta, A.D., Yao-Ping Chen, Menezes, N., Wong, D.F., Pilegg, L.T.

“…Buffers in clock trees introduce two additional sources of skew: the first source of skew is the effect of process variations on buffer delays. The second…”
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Intelligent RAM (IRAM): the industrial setting, applications, and architectures Autor Patterson, D., Asanovic, K., Brown, A., Fromm, R., Golbus, J., Gribstad, B., Keeton, K., Kozyrakis, C., Martin, D., Perissakis, S., Thomas, R., Treuhaft, N., Yelick, K.

“…The goal of intelligent RAM (IRAM) is to design a cost-effective computer by designing a processor in a memory fabrication process, instead of in a…”
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