Suchergebnisse - "IEEE transactions on computer-aided design of integrated circuits and systems"

Novel Techniques for High-Sensitivity Hardware Trojan Detection Using Thermal and Power Maps von Nowroz, Abdullah Nazma, Kangqiao Hu, Koushanfar, Farinaz, Reda, Sherief

“… Hardware Trojans are malicious alterations or injections of unwanted circuitry to integrated circuits (ICs) by untrustworthy factories. They render great …”
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Reliable Hybrid Small-Signal Modeling of GaN HEMTs Based on Particle-Swarm-Optimization von Hussein, Ahmed S., Jarndal, Anwar H.

“… This paper presents an efficient parameter extraction method applied to GaN high electron mobility transistors. The procedure only relies on <inline-formula> …”
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Online Reset for Signal Temporal Logic Monitoring von Zhang, Zhenya, Arcaini, Paolo, Xie, Xuan

“… Online monitoring is a popular validation approach in which the temporal behavior of a system is checked to assess whether it satisfies a given specification …”
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A Robustness-Based Confidence Measure for Hybrid System Falsification von Takisaka, Toru, Zhang, Zhenya, Arcaini, Paolo, Hasuo, Ichiro

“… Verification of hybrid systems is very challenging, if not impossible, due to their continuous dynamics that leads to infinite state space. As a …”
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A Robustness-Based Confidence Measure for Hybrid System Falsification von Toru Takisaka, Zhenya Zhang, Paolo Arcaini, Ichiro Hasuo

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Dedicated Instruction Set for Pattern-based Data Transfers: an Experimental Validation on Systems Containing In-Memory Computing Units von Mambu, Kevin, Charles, Henri-Pierre, Kooli, Maha

“… In-Memory Computing (IMC) aims at solving the performance gap between CPU and memories introduced by the memory wall. However, general-purpose IMC does not …”
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Potential Trigger Detection for Hardware Trojans von Zou, Minhui, Cui, Xiaotong, Shi, Liang, Wu, Kaijie

“… Due to the globalization trend of IC industry, more and more chips are designed and/or fabricated by foreign companies and foundries. Among all the …”
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Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints von Chen, Yu-Guang, Wen, Wan-Yu, Shi, Yiyu, Hon, Wing-Kai, Chang, Shih-Chieh

“… In 3-D integrated circuits, through silicon via (TSV) is a critical enabling technique to provide vertical connections. However, it may suffer from many …”
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MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis von Rajaram, Anand, Pan, David Z

“… Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource …”
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Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods von Kodama, Chikaaki, Ichikawa, Hirotaka, Nakayama, Koichi, Nakajima, Fumiharu, Nojima, Shigeki, Kotani, Toshiya, Ihara, Takeshi, Takahashi, Atsushi

“… Although self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all …”
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Finite memory test response compactors for embedded test applications von Rajski, J., Tyszer, J., Chen Wang, Reddy, S.M.

“… This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses …”
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Testing Resistive Opens and Bridging Faults Through Pulse Propagation von Favalli, M., Metra, C.

“… This paper addresses the problems related to resistive opens and bridging faults that lie out of the most critical paths. These faults cannot be detected by …”
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NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning von Chen, Pai-Yu, Peng, Xiaochen, Yu, Shimeng

“… Neuro-inspired architectures based on synaptic memory arrays have been proposed for on-chip acceleration of weighted sum and weight update in machine/deep …”
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Delay insertion method in clock skew scheduling von Taskin, B., Kourtev, I.S.

“… This paper describes a delay insertion method that improves the efficiency of clock skew scheduling. It is shown that reconvergent paths limit the improvement …”
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DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters von Zhao, Zhuoran, Barijough, Kamyar Mirzazad, Gerstlauer, Andreas

“… Edge computing has emerged as a trend to improve scalability, overhead, and privacy by processing large-scale data, e.g., in deep learning applications locally …”
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DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training von Peng, Xiaochen, Huang, Shanshi, Jiang, Hongwu, Lu, Anni, Yu, Shimeng

“… DNN+NeuroSim is an integrated framework to benchmark compute-in-memory (CIM) accelerators for deep neural networks, with hierarchical design options from …”
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An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures von Zulehner, Alwin, Paler, Alexandru, Wille, Robert

“… In the past years, quantum computers more and more have evolved from an academic idea to an upcoming reality. IBM's project IBM <inline-formula> <tex-math …”
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TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip von Akopyan, Filipp, Sawada, Jun, Cassidy, Andrew, Alvarez-Icaza, Rodrigo, Arthur, John, Merolla, Paul, Imam, Nabil, Nakamura, Yutaka, Datta, Pallab, Gi-Joon Nam, Taba, Brian, Beakes, Michael, Brezzo, Bernard, Kuang, Jente B., Manohar, Rajit, Risk, William P., Jackson, Bryan, Modha, Dharmendra S.

“… The new era of cognitive computing brings forth the grand challenge of developing systems capable of processing massive amounts of noisy multisensory data …”
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A Triple-Memristor Hopfield Neural Network With Space Multistructure Attractors and Space Initial-Offset Behaviors von Lin, Hairong, Wang, Chunhua, Yu, Fei, Hong, Qinghui, Xu, Cong, Sun, Yichuang

“… Memristors have recently demonstrated great promise in constructing memristive neural networks with complex dynamics. This article proposes a memristive …”
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ChatEDA: A Large Language Model Powered Autonomous Agent for EDA von Wu, Haoyuan, He, Zhuolun, Zhang, Xinyun, Yao, Xufeng, Zheng, Su, Zheng, Haisheng, Yu, Bei

“… The integration of a complex set of electronic design automation (EDA) tools to enhance interoperability is a critical concern for circuit designers. Recent …”
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