Suchergebnisse - "Hardware Integrated circuits Semiconductor memory Dynamic memory"

Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology von Seshadri, Vivek, Lee, Donghyuk, Mullins, Thomas, Hassan, Hasan, Boroumand, Amirali, Kim, Jeremie, Kozuch, Michael A., Mutlu, Onur, Gibbons, Phillip B., Mowry, Todd C.

“… Many important applications trigger bulk bitwise operations, i.e., bitwise operations on large bit vectors. In fact, recent works design techniques that …”
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DRISA: a DRAM-based Reconfigurable In-Situ Accelerator von Li, Shuangchen, Niu, Dimin, Malladi, Krishna T., Zheng, Hongzhong, Brennan, Bob, Xie, Yuan

“… Data movement between the processing units and the memory in traditional von Neumann architecture is creating the "memory wall" problem. To bridge the gap, two …”
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Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques von Kim, Jeremie S., Patel, Minesh, Yaglikci, A. Giray, Hassan, Hasan, Azizi, Roknoddin, Orosa, Lois, Mutlu, Onur

“… RowHammer is a circuit-level DRAM vulnerability, first rigorously analyzed and introduced in 2014, where repeatedly accessing data in a DRAM row can cause bit …”
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Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems von O'Connor, Mike, Chatterjee, Niladrish, Lee, Donghyuk, Wilson, John, Agrawal, Aditya, Keckler, Stephen W., Dally, William J.

“… Future GPUs and other high-performance throughput processors will require multiple TB/s of bandwidth to DRAM. Satisfying this bandwidth demand within an …”
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QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips von Olgun, Ataberk, Patel, Minesh, Yaglikci, A. Giray, Luo, Haocong, Kim, Jeremie S., Nisa Bostanci, F., Vijaykumar, Nandita, Ergin, Oguz, Mutlu, Onur

“… True random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases, including …”
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MuonTrap: Preventing Cross-Domain Spectre-Like Attacks by Capturing Speculative State von Ainsworth, Sam, Jones, Timothy M.

“… The disclosure of the Spectre speculative-execution attacks in January 2018 has left a severe vulnerability that systems are still struggling with how to …”
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Perceptron-Based Prefetch Filtering von Bhatia, Eshan, Chacon, Gino, Pugsley, Seth, Teran, Elvira, Gratz, Paul V., Jimenez, Daniel A.

“… Hardware prefetching is an effective technique for hiding cache miss latencies in modern processor designs. Prefetcher performance can be characterized by two …”
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HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips von Yaglikci, A. Giray, Olgun, Ataberk, Patel, Minesh, Luo, Haocong, Hassan, Hasan, Orosa, Lois, Ergin, Oguz, Mutlu, Onur

“… DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh operations degrade system …”
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Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Spatial Hardware Prefetching von Pakalapati, Samuel, Panda, Biswabandan

“… Hardware prefetching is one of the common off-chip DRAM latency hiding techniques. Though hardware prefetchers are ubiquitous in the commercial machines and …”
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IMP: Indirect memory prefetcher von Xiangyao Yu, Hughes, Christopher J., Satish, Nadathur, Devadas, Srinivas

“… Machine learning, graph analytics and sparse linear algebra-based applications are dominated by irregular memory accesses resulting from following edges in a …”
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Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches von Qureshi, Moinuddin K., Patt, Yale N.

“… This paper investigates the problem of partitioning a shared cache between multiple concurrently executing applications. The commonly used LRU policy …”
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CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off von Luo, Haocong, Shahroodi, Taha, Hassan, Hasan, Patel, Minesh, Yaglikci, A. Giray, Orosa, Lois, Park, Jisung, Mutlu, Onur

“… DRAM is the prevalent main memory technology, but its long access latency can limit the performance of many workloads. Although prior works provide DRAM …”
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CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability von Hassan, Hasan, Patel, Minesh, Kim, Jeremie S., Yaglikci, A. Giray, Vijaykumar, Nandita, Ghiasi, Nika Mansouri, Ghose, Saugata, Mutlu, Onur

“… DRAM has been the dominant technology for architecting main memory for decades. Recent trends in multi-core system design and large-dataset applications have …”
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Making DRAM stronger against row hammering von Mungyu Son, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo

“… Modern DRAM suffers from a new problem called row hammering. The problem is expected to become more severe in future DRAMs mostly due to increased inter-row …”
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Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design von Qureshi, Moinuddin K., Loh, Gabe H.

“… This paper analyzes the design trade-offs in architecting large-scale DRAM caches. Prior research, including the recent work from Loh and Hill, have organized …”
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CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations von Orosa, Lois, Wang, Yaohua, Sadrosadati, Mohammad, Kim, Jeremie S., Patel, Minesh, Puddu, Ivan, Luo, Haocong, Razavi, Kaveh, Gomez-Luna, Juan, Hassan, Hasan, Mansouri-Ghiasi, Nika, Ghose, Saugata, Mutlu, Onur

“… DRAM is the dominant main memory technology used in modern computing systems. Computing systems implement a memory controller that interfaces with DRAM via …”
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Random Fill Cache Architecture von Fangfei Liu, Lee, Ruby B.

“… Correctly functioning caches have been shown to leak critical secrets like encryption keys, through various types of cache side-channel attacks. This nullifies …”
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The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions von Patel, Minesh, Kim, Jeremie S., Mutlu, Onur

“… Modern DRAM-based systems suffer from significant energy and latency penalties due to conservative DRAM refresh standards. Volatile DRAM cells can retain …”
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Detecting and mitigating data-dependent DRAM failures by exploiting current memory content von Khan, Samira, Wilkerson, Chris, Wang, Zhe, Alameldeen, Alaa R., Lee, Donghyuk, Mutlu, Onur

“… DRAM cells in close proximity can fail depending on the data content in neighboring cells. These failures are called data-dependent failures. Detecting and …”
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Base-delta-immediate compression: Practical data compression for on-chip caches von Pekhimenko, Gennady, Seshadri, Vivek, Mutlu, Onur, Kozuch, Michael A., Gibbons, Phillip B., Mowry, Todd C.

“… Cache compression is a promising technique to increase on-chip cache capacity and to decrease on-chip and off-chip bandwidth usage. Unfortunately, directly …”
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