Výsledky vyhľadávania - "Hardware Integrated circuits Reconfigurable logic and FPGAs Hardware accelerators"

Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology Autor Seshadri, Vivek, Lee, Donghyuk, Mullins, Thomas, Hassan, Hasan, Boroumand, Amirali, Kim, Jeremie, Kozuch, Michael A., Mutlu, Onur, Gibbons, Phillip B., Mowry, Todd C.

“…Many important applications trigger bulk bitwise operations, i.e., bitwise operations on large bit vectors. In fact, recent works design techniques that…”
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Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration Autor Genc, Hasan, Kim, Seah, Amid, Alon, Haj-Ali, Ameer, Iyer, Vighnesh, Prakash, Pranav, Zhao, Jerry, Grubb, Daniel, Liew, Harrison, Mao, Howard, Ou, Albert, Schmidt, Colin, Steffl, Samuel, Wright, John, Stoica, Ion, Ragan-Kelley, Jonathan, Asanovic, Krste, Nikolic, Borivoje, Shao, Yakun Sophia

“…DNN accelerators are often developed and evaluated in isolation without considering the cross-stack, system-level effects in real-world environments. This…”
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GAMMA: Automating the HW Mapping of DNN Models on Accelerators via Genetic Algorithm Autor Kao, Sheng-Chun, Krishna, Tushar

“…DNN layers are multi-dimensional loops that can be ordered, tiled, and scheduled in myriad ways across space and time on DNN accelerators. Each of these…”
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ANT: Exploiting Adaptive Numerical Data Type for Low-bit Deep Neural Network Quantization Autor Guo, Cong, Zhang, Chen, Leng, Jingwen, Liu, Zihan, Yang, Fan, Liu, Yunxin, Guo, Minyi, Zhu, Yuhao

“…Quantization is a technique to reduce the computation and memory cost of DNN models, which are getting increasingly large. Existing quantization solutions use…”
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Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks Autor Boroumand, Amirali, Ghose, Saugata, Akin, Berkin, Narayanaswami, Ravi, Oliveira, Geraldo F., Ma, Xiaoyu, Shiu, Eric, Mutlu, Onur

“…Emerging edge computing platforms often contain machine learning (ML) accelerators that can accelerate inference for a wide range of neural network (NN)…”
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CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators Autor Boroumand, Amirali, Ghose, Saugata, Patel, Minesh, Hassan, Hasan, Lucia, Brandon, Ausavarungnirun, Rachata, Hsieh, Kevin, Hajinazar, Nastaran, Malladi, Krishna T., Zheng, Hongzhong, Mutlu, Onur

“…Specialized on-chip accelerators are widely used to improve the energy efficiency of computing systems. Recent advances in memory technology have enabled…”
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Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design Autor Fan, Hongxiang, Chau, Thomas, Venieris, Stylianos I., Lee, Royson, Kouris, Alexandros, Luk, Wayne, Lane, Nicholas D., Abdelfattah, Mohamed S.

“…Attention-based neural networks have become pervasive in many AI tasks. Despite their excellent algorithmic performance, the use of the attention mechanism and…”
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NAAS: Neural Accelerator Architecture Search Autor Lin, Yujun, Yang, Mengtian, Han, Song

“…Data-driven, automatic design space exploration of neural accelerator architecture is desirable for specialization and productivity. Previous frameworks focus…”
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Laconic Deep Learning Inference Acceleration Autor Sharify, Sayeh, Lascorz, Alberto Delmas, Mahmoud, Mostafa, Nikolic, Milos, Siu, Kevin, Stuart, Dylan Malone, Poulos, Zissis, Moshovos, Andreas

“…We present a method for transparently identifying ineffectual computations during inference with Deep Learning models. Specifically, by decomposing…”
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DFX: A Low-latency Multi-FPGA Appliance for Accelerating Transformer-based Text Generation Autor Hong, Seongmin, Moon, Seungjae, Kim, Junsoo, Lee, Sungjae, Kim, Minsub, Lee, Dongsoo, Kim, Joo-Young

“…Transformer is a deep learning language model widely used for natural language processing (NLP) services in datacenters. Among transformer models, Generative…”
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PolySA: Polyhedral-Based Systolic Array Auto-Compilation Autor Cong, Jason, Wang, Jie

“…Automatic systolic array generation has long been an interesting topic due to the need to reduce the lengthy development cycles of manual designs. Existing…”
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CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network Accelerator Autor Sunny, Febin, Mirza, Asif, Nikdast, Mahdi, Pasricha, Sudeep

“…Domain-specific neural network accelerators have seen growing interest in recent years due to their improved energy efficiency and performance compared to CPUs…”
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Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks Autor Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong

“…With the recent advancement of multilayer convolutional neural networks (CNN), deep learning has achieved amazing success in many areas, especially in visual…”
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SODA: Stencil with Optimized Dataflow Architecture Autor Chi, Yuze, Cong, Jason, Wei, Peng, Zhou, Peipei

“…Stencil computation is one of the most important kernels in many application domains such as image processing, solving partial differential equations, and…”
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MnnFast: A Fast and Scalable System Architecture for Memory-Augmented Neural Networks Autor Jang, Hanhwi, Kim, Joonsung, Jo, Jae-Eon, Lee, Jaewon, Kim, Jangwoo

“…Memory-augmented neural networks are getting more attention from many researchers as they can make an inference with the previous history stored in memory…”
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Efficient Hardware Acceleration of CNNs using Logarithmic Data Representation with Arbitrary log-base Autor Vogel, Sebastian, Liang, Mengyu, Guntoro, Andre, Stechele, Walter, Ascheid, Gerd

“…Efficient acceleration of Deep Neural Networks is a manifold task. In order to save memory requirements and reduce energy consumption we propose the use of…”
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LLMCompass: Enabling Efficient Hardware Design for Large Language Model Inference Autor Zhang, Hengrui, Ning, August, Prabhakar, Rohan Baskar, Wentzlaff, David

“…The past year has witnessed the increasing popularity of Large Language Models (LLMs). Their unprecedented scale and associated high hardware cost have impeded…”
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TGPA: Tile-Grained Pipeline Architecture for Low Latency CNN Inference Autor Wei, Xuechao, Liang, Yun, Li, Xiuhong, Yu, Cody Hao, Zhang, Peng, Cong, Jason

“…FPGAs are more and more widely used as reconfigurable hardware accelerators for applications leveraging convolutional neural networks (CNNs) in recent years…”
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Energy-Efficient Video Processing for Virtual Reality Autor Leng, Yue, Chen, Chi-Chun, Sun, Qiuyue, Huang, Jian, Zhu, Yuhao

“…Virtual reality (VR) has huge potential to enable radically new applications, behind which spherical panoramic video processing is one of the backbone…”
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MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition Autor Qin, Yubin, Wang, Yang, Zhao, Zhiren, Yang, Xiaolong, Zhou, Yang, Wei, Shaojun, Hu, Yang, Yin, Shouyi

“…Large language models (LLMs) have been showing surprising performance in processing language tasks, bringing a new prevalence to deploy LLM from cloud to edge…”
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