Výsledky vyhledávání - "Hardware Integrated circuits Logic circuits Sequential circuits"

PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT Autor Chao, Zhiteng, Zhang, Xindi, Zhang, Xinyu, Mu, Jianan, Liu, Zizhen, Liang, Shengwen, Cai, Shaowei, Ye, Jing, Li, Xiaowei, Li, Huawei

“…In automatic test pattern generation (ATPG), SAT-based methods are typically used to complement structural approaches, especially for addressing hard-to-detect…”
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Parallel Dynamic Partitioning for Datapath Combinational Equivalence Checking Autor Zhou, Shuai, Zhang, Weikang, Zhang, Xindi, Jiang, Zite, You, Haihang, Cai, Shaowei

“…Combinational Equivalence Checking (CEC) is a crucial technique in electronic design automation for verifying the functional equivalence of combinational…”
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qSeq: Full Algorithmic and Tool Support for Synthesizing Sequential Circuits in Superconducting SFQ Technology Autor Pasandi, Ghasem, Pedram, Massoud

“…Synthesizing general nonlinear sequential circuits in superconducting Single Flux Quantum (SFQ) technology is a challenging task involving the proper leveling…”
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Optimal circuits for parallel bit reversal Autor Ren Chen, Prasanna, Viktor K.

“…In this paper, we develop novel parallel circuit designs for calculating the bit reversal. To perform bit reversal on 2 n data words, the designs take 2 k (k…”
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Synthesis of statically analyzable accelerator networks from sequential programs Autor Shaoyi Cheng, Wawrzynek, John

“…This paper describes a general framework for transforming a sequential program into a network of processes, which are then converted to hardware accelerators…”
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Minimizing area and power of sequential CMOS circuits using threshold decomposition Autor Kulkarni, Niranjan, Nukala, Nishant, Vrudhula, Sarma

“…This paper describes the design of a standard cell library of differential mode threshold gates, referred to as a Threshold Logic Latch or TLL, and new…”
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SeGen: Automatic Topology Generator for Sequencing Elements Autor Kang, Kyounghun, Jung, Wanyeong

“…Sequencing elements, such as flip-flops (FFs), significantly impact the speed, size, and power consumption of digital integrated circuits. Despite numerous…”
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Efficient generation of counterexamples and witnesses in symbolic model checking Autor Clarke, E. M., Grumberg, O., McMillan, K. L., Zhao, X.

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Security against hardware Trojan through a novel application of design obfuscation Autor Chakraborty, R.S., Bhunia, S.

“…Malicious hardware Trojan circuitry inserted in safety-critical applications is a major threat to national security. In this work, we propose a novel…”
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Power gating applied to MP-SoCs for standby-mode power management Autor Flynn, David

“…Complex SoCs from servers to intelligent sensors are increasingly built up from heterogeneous IP cores and subsystems. Accelerator blocks or additional…”
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Conflict driven learning in a quantified Boolean Satisfiability solver Autor Zhang, Lintao, Malik, Sharad

“…Within the verification community, there has been a recent increase in interest in Quantified Boolean Formula evaluation (QBF) as many interesting sequential…”
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Dynamic Verification of Sequential Consistency Autor Meixner, Albert, Sorin, Daniel J.

“…In this paper, we develop the first feasibly implementable scheme for end-to-end dynamic verification of multithreaded memory systems. For multithreaded…”
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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients Autor Badaroglu, Mustafa, Tiri, Kris, Donnay, StÉphane, Wambacq, Piet, Man, Hugo De, Verbauwhede, Ingrid, Gielen, Georges

“…In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge, therefore they generate substrate…”
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Skewed flip-flop transformation for minimizing leakage in sequential circuits Autor Seomun, Jun, Kim, Jaehyun, Shin, Youngsoo

“…Mixed Vt has been widely used to control leakage without affecting circuit performance. However, current approaches target the combinational circuits even…”
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Polynomial arithmetic using sequential stochastic logic Autor Saraf, Naman, Bazargan, Kia

“…We present the design of stochastic computing systems based on sequential logic to implement arbitrary polynomial functions. Stochastic computing is an…”
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Automatic functional test generation using the extended finite state machine model Autor Cheng, Kwang Ting, Krishnakumar, A. S.

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Efficient Solution of Language Equations Using Partitioned Representations Autor Mishchenko, Alan, Brayton, Robert, Jiang, Roland, Villa, Tiziano, Yevtushenko, Nina

“…A class of discrete event synthesis problems can be reduced to solving language equations f X S, where F is the fixed component and S the specification…”
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Combining deterministic and genetic approaches for sequential circuit test generation Autor Rudnick, Elizabeth M., Patel, Janak H.

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Efficient Preimage Computation Using A Novel Success-Driven ATPG Autor Sheng, Shuo, Hsiao, Michael

“…Preimage computation is a key step in formal verification. Pure OBDD-based symbolic method is vulnerable to the space-explosion problem. On the other hand,…”
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Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG Autor Ichihara, Hideyuki, Inoue, Tomoo

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