Výsledky vyhledávání - "Hardware Integrated circuits Logic circuits Design modules and hierarchy"

Tartan: Microarchitecting a Robotic Processor Autor Bakhshalipour, Mohammad, Gibbons, Phillip B.

“…This paper presents Tartan, a CPU architecture designed for a wide range of robotic applications. Tartan provides architectural support for common robotic…”
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The design and use of simplepower: a cycle-accurate energy estimation tool Autor Ye, W., Vijaykrishnan, N., Kandemir, M., Irwin, M. J.

“…In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for ev aluating the effect of high-level algorithmic, architectural,…”
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Lower power by voltage stacking: A fine-grained system design approach Autor Blutman, Kristof, Kapoor, Ajay, Martinez, Jacinto Garcia, Fatemi, Hamed, de Gyvez, Jose Pineda

“…Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency…”
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VEAL: Virtualized Execution Accelerator for Loops Autor Clark, Nathan, Hormati, Amir, Mahlke, Scott

“…Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific…”
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An O(m+n)-Space Spatiotemporal Denoising Filter with Cache-Like Memories for Dynamic Vision Sensors Autor Zhao, Qinghang, Wang, Jiaqi, Ji, Yixi, Wu, Jinjian, Shi, Guangming

“…Dynamic vision sensor (DVS) is novel neuromorphic imaging device that generates asynchronous events. Despite the high temporal resolution and high dynamic…”
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FSMM: An Efficient Matrix Multiplication Accelerator Supporting Flexible Sparsity Autor Qiao, Yuxuan, Yang, Fan, Zhang, Yecheng, Xiong, Xiankui, Yao, Xiao, Yao, Haidong

“…Sparse matrix multiplication is a critical operation in deep learning. However, matrix sparsity leads to irregular data flow, which would degrade the…”
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Influence of compiler optimizations on system power Autor Kandemir, M., Vijaykrishnan, N., Irwin, M. J., Ye, W.

“…High-level compiler optimizations ha ve been widely used to ac hiev e speedups on array-based codes. Su ch optimizations are becoming increasingly important in…”
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Achieving Out-of-Order Performance with Almost In-Order Complexity Autor Tseng, Francis, Patt, Yale N.

“…There is still much performance to be gained by out-of-order processors with wider issue widths. However, traditional methods of increasing issue width do not…”
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Enforcing architectural contracts in high-level synthesis Autor Patil, Nikhil, Bansal, Ankit, Chiou, Derek

“…We present a high-level synthesis technique that takes as input two orthogonal descriptions: (a) a behavioral architectural contract between the implementation…”
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Operating system based software generation for systems-on-chip Autor Desmet, Dirk, Verkest, D., De Man, Hugo

“…In this paper we propose a system-level design environment, aimed at System-on-Chip (SOC) designs, including real-time embedded software. While many SOC…”
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An N-Way Group Association Architecture and Sparse Data Group Association Load Balancing Algorithm for Sparse CNN Accelerators Autor Wang, Jingyu, Yuan, Zhe, Liu, Ruoyang, Yang, Huazhong, Liu, Yongpan

“…In recent years, ASIC CNN Accelerators have attracted great attention among researchers for the high performance and energy efficiency. Some former works…”
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Memory aware compilation through accurate timing extraction Autor Grun, Peter, Dutt, Nikil, Nicolau, Alex

“…Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode)…”
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Evaluation of a high performance code compression method Autor Lefurgy, Charles, Piccininni, Eva, Mudge, Trevor

“…Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression…”
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Bus encoding for low-power high-performance memory systems Autor Chang, Naehyuck, Kim, Kwanho, Cho, Jinsung

“…High-performance memory buses consume large energy as they include termination networks, BiCMOS and/or open-drain output. This paper introduces power reduction…”
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Compiling Esterel into sequential code Autor Edwards, Stephen A.

“…Embedded real-time software systems often need fine-grained parallelism and precise control over time, things typical real-time operating systems do not…”
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Address code generation for digital signal processors Autor Udayanarayanan, Sathishkumar, Chakrabarti, Chaitali

“…In this paper we propose a procedure to generate code with minimum number of addressing instructions. We analyze different methods of generating addressing…”
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Microcoded Architectures for Ion-Tap Quantum Computers Autor Kreger-Stickles, Lucas, Oskin, Mark

“…In this paper we present the first ever systematic design space exploration of microcoded software fault tolerant ion-trap quantum computers. This exploration…”
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Utilizing memory bandwidth in DSP embedded processors Autor Gebotys, Catherine H.

“…This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently…”
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Low-cost branch folding for embedded applications with small tight loops Autor Lee, Lea Hwang, Scott, Jeff, Moyer, Bill, Arends, John

“…Many portable and embedded applications are characterized by spending a large fraction of execution time on small program loops. To improve performance, many…”
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A comparison of full and partial predicated execution support for ILP processors Autor Mahlke, Scott A., Hank, Richard E., McCormick, James E., August, David I., Hwu, Wen-Mei W.

“…One can effectively utilize predicated execution to improve branch handling in instruction-level parallel processors. Although the potential benefits of…”
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