Výsledky vyhledávání - "Hardware Integrated circuits Logic circuits Combinational circuits"

TransSizer: A Novel Transformer-Based Fast Gate Sizer Autor Nath, Siddhartha, Pradipta, Geraldo, Hu, Corey, Yang, Tian, Khailany, Brucek, Ren, Haoxing

“…Gate sizing is a fundamental netlist optimization move and researchers have used supervised learning-based models in gate sizers. Recently, Reinforcement…”
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Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery Autor Chung, Sehyeon, Hwang, Hyun-Chul, Kim, Byung Su, Lee, Jaeha, Kang, Kunhyuk, Kim, Taewhan

“…As the process technology advances, reducing the leakage power as much as possible is one of the utmost challenging tasks in chip implementation. Utilizing…”
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EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components Autor Wang, Mingjun, Wang, Hui, Mu, Jianan, Zhang, Xinyu, Sun, Bin, Wen, Yihan, Liu, Zizhen, Gu, Feng, Gao, Jun, Liang, Shengwen, Ye, Jing, Li, Xiaowei, Li, Huawei

“…As functional safety of electronic chips gains importance in autonomous vehicles and aerospace, standards like ISO 26262 mandate high diagnostic coverage,…”
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Logic Restructuring with Preserved Logic Blocks Autor Lee, Siang-Yun, Riener, Heinz, Richter, Sascha, Sood, Ankush

“…During technology mapping, complex cells such as adders and multiplexers are often available in the standard cell library, which helps improve the final PPA…”
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Routability-aware Packing for High-density Nonvolatile FPGAs Autor Zheng, Huichuan, Xiong, Yuqing, Zuo, Jian, Zhang, Hao, Jia, Zhenge, Zhao, Mengying

“…Nonvolatile field-programmable gate arrays (NVFPGAs) can use multi-level cell (MLC) nonvolatile memories (NVMs) to enhance their logic density. However, the…”
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Emerging Reconfigurable Nanotechnologies: Can they support Future Electronics? Autor Rai, Shubham, Srinivasa, Srivatsa, Cadareanu, Patsy, Xunzhao Yin, Hu, Xiaobo Sharon, Gaillardon, Pierre-Emmanuel, Narayanan, Vijaykrishnan, Kumar, Akash

“…Several emerging reconfigurable technologies have been explored in recent years offering device level runtime reconfigurability. These technologies offer the…”
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Design Space Exploration of Multi-output Logic Function Approximations Autor Echavarria, Jorge, Wildermann, Stefan, Teich, Jurgen

“…Approximate Computing has emerged as a design paradigm that allows to decrease hardware costs by reducing the accuracy of the computation for applications that…”
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ASPPLN: Accelerated Symbolic Probability Propagation in Logic Network Autor Xiao, Weihua, Qian, Weikang

“…Probability propagation is an important task used in logic network analysis, which propagates signal probabilities from its primary inputs to its primary…”
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Canonicalization of Threshold Logic Representation and Its Applications Autor Lee, Siang-Yun, Lee, Nian-Ze, Jiang, Jie-Hong R.

“…Threshold logic functions gain revived attention due to their connection to neural networks employed in deep learning. Despite prior endeavors in the…”
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Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics Autor Shiomi, Jun, Kotsugi, Shuya, Dong, Boyu, Onodera, Hidetoshi, Shinya, Akihiko, Notomi, Masaya

“…A tamper-resistant logical operation method based on integrated nanophotonics is proposed focusing on electromagnetic side-channel attacks. In the proposed…”
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IC/IP Piracy Assessment of Reversible Logic Autor Saeed, Samah Mohamed, Cui, Xiaotong, Zulehner, Alwin, Wille, Robert, Drechsler, Rolf, Wu, Kaijie, Karri, Ramesh

“…Reversible logic is a building block for adiabatic and quantum computing in addition to other applications. Since common functions are non-reversible, one…”
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Energy efficient implementation of parallel CMOS multipliers with improved compressors Autor Baran, Dursun, Aktan, Mustafa, Oklobdzija, Vojin G.

“…Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16×16-bit Booth and Non-Booth multipliers are analyzed in energy…”
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Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA Autor Doi, Ryutaro, Yu, Jaehoon, Hashimoto, Masanori

“…FPGA that utilizes via-switches, which are a kind of nonvolatile resistive RAMs, for crossbar implementation is attracting attention due to higher integration…”
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The synthesis of robust polynomial arithmetic with stochastic logic Autor Qian, Weikang, Riedel, Marc D.

“…As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is…”
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Reconfigurable multi-function logic based on graphene p-n junctions Autor Tanachutiwat, Sansiri, Ji Ung Lee, Wei Wang, Chun Yung Sung

“…In this paper, we introduce a novel reconfigurable graphene logic based on graphene p-n junctions. In this logic device, switching is accomplished by using…”
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Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications Autor Zhang, Lintao, Malik, Sharad

“…As the use of SAT solvers as core engines in EDA applications grows, it becomes increasingly important to validate their correctness. In this paper, we…”
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LAG-Sizer: A Novel Gate Sizer Based on Leak Generative Adversarial Network with Feature Fusion Autor Zhang, Zhanhua, Ding, Wenjing, He, Guoqing, Cao, Peng

“…Gate sizing is an NP-hard problem to achieve Performance, Power and Area (PPA) optimization. Recently proposed learning-based approaches struggle to overcome…”
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Verification of Proofs of Unsatisfiability for CNF Formulas Autor Goldberg, Evgueni, Novikov, Yakov

“…As SAT-algorithms become more and more complex, there is little chance of writing a SAT-solver that is free of bugs. So it is of great importance to be able to…”
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Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits Autor Dhillon, Yuvraj Singh, Diril, Abdulkadir Utku, Chatterjee, Abhijit

“…Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node…”
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Single stage static level shifter design for subthreshold to I/O voltage conversion Autor Lin, Yi-Shiang, Sylvester, Dennis M.

“…A static subthreshold to I/O voltage level shifter is proposed. The proposed circuit employs a diode-connected pull-up transistor stack and a feedback…”
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