Search Results - "Hardware Integrated circuits Logic circuits Arithmetic and datapath circuits"

Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization by Liu, Meng-Yun, Lai, Yu-Cheng, Mak, Wai-Kei, Wang, Ting-Chi

“… bits. To maximize the FF merging rate (and hence to minimize the final amount of clock sinks), our approach will first perform aggressive FF merging subject to timing constraints…”
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Formal Verification of Restoring Dividers made Fast and Simple by Dasari, Jiteshri, Ciesielski, Maciej

“…The paper describes a formal verification method for hardware implementation of restoring divider circuits. The method is based on setting select signals to…”
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Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures by Roy, Subhendu, Choudhury, Mihir, Puri, Ruchir, Pan, David Z.

“… For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of prefix graph subject to constraints like…”
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Multiple tunable constant multiplications: algorithms and applications by Aksoy, Levent, Costa, Eduardo, Flores, Paulo, Monteiro, José

“… for the multiplication of multiple constants by an input variable, has been the subject of great interest since the complexity of many digital signal processing (DSP…”
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Architectural synthesis of performance-driven multipliers with accumulator interleaving by Ghosh, Debabrata, Nandy, S. K., Sadayappan, P., Parthasarathy, K.

“…VLSI multipliers assume different characteristics in terms of latency, throughput and area for different target applications. This paper proposes a methodology…”
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The program decision logic approach to predicated execution by August, David I., Sias, John W., Puiatti, Jean-Michel, Mahlke, Scott A., Connors, Daniel A., Crozier, Kevin M., Hwu, Wen-mei W.

“… Eliminating inefficiencies in handling branch instructions and exploiting ILP has been the subject of much research…”
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Resource constrained dataflow retiming heuristics for VLIW ASIPs by Jacome, M., de Veciana, G., Akturan, C.

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