Suchergebnisse - "Hardware Integrated circuits Logic circuits"

Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization von Liu, Meng-Yun, Lai, Yu-Cheng, Mak, Wai-Kei, Wang, Ting-Chi

“… bits. To maximize the FF merging rate (and hence to minimize the final amount of clock sinks), our approach will first perform aggressive FF merging subject to timing constraints …”
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Formal Verification of Restoring Dividers made Fast and Simple von Dasari, Jiteshri, Ciesielski, Maciej

“… The paper describes a formal verification method for hardware implementation of restoring divider circuits. The method is based on setting select signals to …”
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Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures von Roy, Subhendu, Choudhury, Mihir, Puri, Ruchir, Pan, David Z.

“… For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of prefix graph subject to constraints like …”
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Multiple tunable constant multiplications: algorithms and applications von Aksoy, Levent, Costa, Eduardo, Flores, Paulo, Monteiro, José

“… for the multiplication of multiple constants by an input variable, has been the subject of great interest since the complexity of many digital signal processing (DSP …”
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In Medio Stat Virtus: Combining Boolean and Pattern Matching von Radi, Gianluca, Calvino, Alessandro Tempia, De Micheli, Giovanni

“… This process is performed by means of local replacements that are extracted by matching sections of the subject graph to library cells …”
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The program decision logic approach to predicated execution von August, David I., Sias, John W., Puiatti, Jean-Michel, Mahlke, Scott A., Connors, Daniel A., Crozier, Kevin M., Hwu, Wen-mei W.

“… Eliminating inefficiencies in handling branch instructions and exploiting ILP has been the subject of much research …”
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A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation von Li, Lijun, Tropper, Carl

“… Many partitioning algorithms have been proposed for distributed VLSI simulation. Typically, they make use of a gate level netlist, and attempt to achieve a minimal cut size subject to a load balance constraint …”
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Optimal clustering for delay minimization von Rajaraman, Rajmohan, Wong, D. F.

“… This paper addresses the problem of circuit clustering for delay minimization, subject to capacity constraints …”
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Resource constrained dataflow retiming heuristics for VLIW ASIPs von Jacome, M., de Veciana, G., Akturan, C.

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Advanced technology mapping for standard-cell generators von Correia, Vinícius, Reis, André

“… In the covering step, the cell that leads to the smaller depth increase is chosen. Depth calculation is not limited to the subject tree and takes into account all previously mapped trees representing sub-expressions used as inputs …”
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Optimum design of reliable IC power networks having general graph topologies von Chowdhury, S.

“… Algorithms are developed to determine the widths of the power and ground routes so that the area required by the routes is minimized subject to the constraints imposed …”
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Boolean Technology Mapping Based on Logic Decomposition von Damiani, Maurizio, Selchenko, Andrei Y.

“… Decomposition information is also embedded in the representation of leaf-dags of the subject graph …”
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Architectural synthesis of performance-driven multipliers with accumulator interleaving von Ghosh, Debabrata, Nandy, S. K., Sadayappan, P., Parthasarathy, K.

“… VLSI multipliers assume different characteristics in terms of latency, throughput and area for different target applications. This paper proposes a methodology …”
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Electrical optimization of PLAs von Hedlund, Kye S.

“… Algorithms are presented for: a) minimization of delay through the PLA b) minimization of power consumption subject to a bound on maximum delay …”
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