Výsledky vyhledávání - "Hardware Hardware validation Functional verification Simulation and emulation"

Out-of-order parallel simulation for ESL design Autor Chen, Weiwei, Han, Xu, Dömer, Rainer

“… Subject to automatic static data analysis at compile time and table-based decisions at run time, threads can be issued early which reduces the idle time of available cores. Our experiments show high performance gains in simulation speed with only a small increase of compile time…”
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A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation Autor Li, Lijun, Tropper, Carl

“…Many partitioning algorithms have been proposed for distributed VLSI simulation. Typically, they make use of a gate level netlist, and attempt to achieve a minimal cut size subject to a load balance constraint…”
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A framework for scheduling multi-rate circuit simulation Autor Ng, A. P.-C., Visvanathan, V.

“… It is possible to show that the problem of scheduling the subcircuits subject to these constraints…”
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On modeling integrated design environments Autor Hübel, Christoph, Ruland, Detlev, Siepmann, Ernst

“…) design subject model. The design structure model is introduced for modeling on a higher level of abstraction exactly those aspects of design objects which are necessary for design methodology management. The applied concept is called design object abstraction…”
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A technology independent block extraction algorithm Autor Luellau, F., Hoepken, T., Barke, E.

“… The algorithm is fully technology independent. The size of the blocks is not subject to any restrictions…”
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