Výsledky vyhledávání - "Hardware Hardware validation Functional verification Simulation and emulation"

RFUZZ: Coverage-Directed Fuzz Testing of RTL on FPGAs Autor Laeufer, Kevin, Koenig, Jack, Kim, Donggyu, Bachrach, Jonathan, Sen, Koushik

“…Dynamic verification is widely used to increase confidence in the correctness of RTL circuits during the pre-silicon design phase. Despite numerous attempts…”
Získat plný text

An Efficient Algorithm for Sparse Quantum State Preparation Autor Gleinig, Niels, Hoefler, Torsten

“…Generating quantum circuits that prepare specific states is an essential part of quantum compilation. Algorithms that solve this problem for general states…”
Získat plný text

Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation Autor Tsai, Yuan-Hung, Jiang, Jie-Hong R., Jhang, Chiao-Shan

“…Recent advancements in quantum technologies shed light on viable quantum computation in near future. Quantum circuit simulation plays a key role in the…”
Získat plný text

EPIC: Error PredIction and Correction for Power-Efficient Voltage Underscaling Multiply-Accumulate Unit Autor Wu, Tongjing, Hu, Xiaolu, Li, Tong, Liu, Siting, Wang, Hui, He, Weifeng, Mao, Zhigang, Jiang, Honglan

“…Matrix multiplication dominates the power consumption in compute-intensive applications such as deep neural networks (DNNs), spurring intensive investigations…”
Získat plný text

EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components Autor Wang, Mingjun, Wang, Hui, Mu, Jianan, Zhang, Xinyu, Sun, Bin, Wen, Yihan, Liu, Zizhen, Gu, Feng, Gao, Jun, Liang, Shengwen, Ye, Jing, Li, Xiaowei, Li, Huawei

“…As functional safety of electronic chips gains importance in autonomous vehicles and aerospace, standards like ISO 26262 mandate high diagnostic coverage,…”
Získat plný text

A Cutting-Edge Parallel Solver for Scalable Power Grid Analysis Using Nested Domain Decomposition Autor Song, Jianfei, Yang, Xiaoyu, Jin, Zhou, Zhuo, Cheng

“…As transistor scaling approaches sub-5 nm technologies, power distribution networks (PDNs) in integrated circuits have grown increasingly complex, with…”
Získat plný text

Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits Autor Herzog, Laura S., Burgholzer, Lukas, Ufrecht, Christian, Scherer, Daniel D., Wille, Robert

“…Despite the continuous advancements in size and robustness of real quantum devices, reliable large-scale quantum computers are not yet available. Hence,…”
Získat plný text

Late Breaking Results: Opera: An Open and Efficient Platform for Data-driven Synthesis of Analog Circuits Autor Wang, Shikai, Hu, Yaolong, Yi, Zhiqiang, Chi, Taiyun, Cao, Weidong

“…The front-end synthesis of analog circuits has been a long-standing challenge since the advent of integrated circuits. Many methods, ranging from conventional…”
Získat plný text

Efficient Recycling Subspace Truncation Method for Periodic Small-Signal Analysis Autor Xu, Yuncheng, Yang, Fan, Su, Yangfeng

“…Periodic small-signal analysis is crucial but timeconsuming in RF simulation, since it may deal with many frequency points. While the Krylov subspace recycling…”
Získat plný text

Swift or Exact? Boosting Efficient Microarchitecture DSE via Multi-fidelity Partial Order Prediction Autor Liu, Hang, Geng, Hao, He, Zhuolun, Sun, Qi, Zhuo, Cheng

“…A significant challenge in microarchitecture design space exploration (DSE) lies in the time-intensive synthesis and simulation process, making rapid design…”
Získat plný text

YAP: Yield Modeling and Simulation for Advanced Packaging Autor Chen, Zhichao, Gupta, Puneet

“…Three-dimensional integration technologies present a promising path forward for extending Moore's law, facilitating high-density interconnects between chips…”
Získat plný text

Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks Autor Bertuletti, Marco, Zhang, Yichao, Abdollahpour, Mahdi, Riedel, Samuel, Vanelli-Coralli, Alessandro, Benini, Luca

“…The fast-rising demand for wireless bandwidth [1] requires rapid evolution of high-performance baseband processing infrastructure. Programmable many-core…”
Získat plný text

Accelerating design-technology co-development using neural compact modeling and data-driven SPICE simulation Autor Lee, Yongjeong, Lee, Seungsoo, Kim, Jeongyeol, Choi, Jungyun, Li, Zhaojie, Wu, Dehuang, Wang, Joddy

“…This paper proposes a new design-technology cooptimization framework that expedites circuit optimization by utilizing the neural compact modeling (NCM) and a…”
Získat plný text

SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation Autor Yu, Ziyang, Xu, Peng, Wang, Zixiao, Zhu, Binwu, Wang, Qipan, Lin, Yibo, Wang, Runsheng, Yu, Bei, Wong, Martin

“…The post-exposure bake (PEB) process is a critical step in semiconductor lithography, directly impacting resist profile accuracy and circuit pattern fidelity…”
Získat plný text

G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks Autor Zeng, Lijie, Sun, Jiatai, Wu, Xiao, Niu, Dan, Wang, Tianshi, Lin, Yibo, Ye, Zuochang, Jin, Zhou

“…The increasing complexity of high-frequency circuits calls for efficient and accurate passive macromodeling techniques. Existing passivity enforcement methods,…”
Získat plný text

Decoupling Analog Circuit Representation from Technology for Behavior-Centric Optimization Autor Li, Jintao, Zhi, Haochang, Xiao, Jiang, Zhu, Keren, Li, Yun

“…Analog IC design is mainly manual and implemented at the device level. A major reason is circuit behavior-extraction. Unlike its digital counterpart, analog IC…”
Získat plný text

PiSPICE: Accelerating Post-Layout SPICE Simulation via Essential Parasitic Identification Autor Jin, Zhou, Li, Jing, Xin, Jian, Zhou, Tianjia, Wu, Xiao, Niu, Dan, Ye, Zuochang

“…As process nodes scale to more advanced technologies, post-layout simulations for integrated circuits have become increasingly complex, involving billions to…”
Získat plný text

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis Autor Li, Wenkai, Lu, Yao, Fang, Wenji, Wang, Jing, Zhang, Qijun, Xie, Zhiyao

“…Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout…”
Získat plný text

Generative Model Based Standard Cell Timing Library Characterization Autor Wu, Hao-Yu, Chang, Hsin-Tzu, Ding, Shiuan-Yun, Jiang, Iris Hui-Ru, Tsao, Benson, Wu, Vinson, Shih, Wei-Kai

“…Accurate cell timing characterization is essential, on which static timing analysis relies to verify timing performance and ensure design robustness across…”
Získat plný text

Self-Attention to Operator Learning-based 3D-IC Thermal Simulation Autor Huang, Zhen, Wang, Hong, Yang, Wenkai, Tang, Muxi, Xie, Depeng, Lin, Ting-Jung, Zhang, Yu, Xing, Wei W., He, Lei

“…Thermal management in 3D ICs is increasingly challenging due to higher power densities. Traditional PDESolving based methods, while accurate, are too slow for…”
Získat plný text