Search Results - "Hardware Hardware validation Functional verification"

RFUZZ: Coverage-Directed Fuzz Testing of RTL on FPGAs by Laeufer, Kevin, Koenig, Jack, Kim, Donggyu, Bachrach, Jonathan, Sen, Koushik

“…Dynamic verification is widely used to increase confidence in the correctness of RTL circuits during the pre-silicon design phase. Despite numerous attempts…”
Get full text

An Efficient Algorithm for Sparse Quantum State Preparation by Gleinig, Niels, Hoefler, Torsten

“…Generating quantum circuits that prepare specific states is an essential part of quantum compilation. Algorithms that solve this problem for general states…”
Get full text

Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation by Tsai, Yuan-Hung, Jiang, Jie-Hong R., Jhang, Chiao-Shan

“…Recent advancements in quantum technologies shed light on viable quantum computation in near future. Quantum circuit simulation plays a key role in the…”
Get full text

EPIC: Error PredIction and Correction for Power-Efficient Voltage Underscaling Multiply-Accumulate Unit by Wu, Tongjing, Hu, Xiaolu, Li, Tong, Liu, Siting, Wang, Hui, He, Weifeng, Mao, Zhigang, Jiang, Honglan

“…Matrix multiplication dominates the power consumption in compute-intensive applications such as deep neural networks (DNNs), spurring intensive investigations…”
Get full text

EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components by Wang, Mingjun, Wang, Hui, Mu, Jianan, Zhang, Xinyu, Sun, Bin, Wen, Yihan, Liu, Zizhen, Gu, Feng, Gao, Jun, Liang, Shengwen, Ye, Jing, Li, Xiaowei, Li, Huawei

“…As functional safety of electronic chips gains importance in autonomous vehicles and aerospace, standards like ISO 26262 mandate high diagnostic coverage,…”
Get full text

A Cutting-Edge Parallel Solver for Scalable Power Grid Analysis Using Nested Domain Decomposition by Song, Jianfei, Yang, Xiaoyu, Jin, Zhou, Zhuo, Cheng

“…As transistor scaling approaches sub-5 nm technologies, power distribution networks (PDNs) in integrated circuits have grown increasingly complex, with…”
Get full text

Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits by Herzog, Laura S., Burgholzer, Lukas, Ufrecht, Christian, Scherer, Daniel D., Wille, Robert

“…Despite the continuous advancements in size and robustness of real quantum devices, reliable large-scale quantum computers are not yet available. Hence,…”
Get full text

Late Breaking Results: Opera: An Open and Efficient Platform for Data-driven Synthesis of Analog Circuits by Wang, Shikai, Hu, Yaolong, Yi, Zhiqiang, Chi, Taiyun, Cao, Weidong

“…The front-end synthesis of analog circuits has been a long-standing challenge since the advent of integrated circuits. Many methods, ranging from conventional…”
Get full text

Swift or Exact? Boosting Efficient Microarchitecture DSE via Multi-fidelity Partial Order Prediction by Liu, Hang, Geng, Hao, He, Zhuolun, Sun, Qi, Zhuo, Cheng

“…A significant challenge in microarchitecture design space exploration (DSE) lies in the time-intensive synthesis and simulation process, making rapid design…”
Get full text

Efficient Recycling Subspace Truncation Method for Periodic Small-Signal Analysis by Xu, Yuncheng, Yang, Fan, Su, Yangfeng

“…Periodic small-signal analysis is crucial but timeconsuming in RF simulation, since it may deal with many frequency points. While the Krylov subspace recycling…”
Get full text

Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications by Ferrandi, Fabrizio, Castellana, Vito Giovanni, Curzel, Serena, Fezzardi, Pietro, Fiorito, Michele, Lattuada, Marco, Minutoli, Marco, Pilato, Christian, Tumeo, Antonino

“…This paper presents the open-source high-level synthesis (HLS) research framework Bambu. Bambu provides a research environment to experiment with new ideas…”
Get full text

YAP: Yield Modeling and Simulation for Advanced Packaging by Chen, Zhichao, Gupta, Puneet

“…Three-dimensional integration technologies present a promising path forward for extending Moore's law, facilitating high-density interconnects between chips…”
Get full text

Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks by Bertuletti, Marco, Zhang, Yichao, Abdollahpour, Mahdi, Riedel, Samuel, Vanelli-Coralli, Alessandro, Benini, Luca

“…The fast-rising demand for wireless bandwidth [1] requires rapid evolution of high-performance baseband processing infrastructure. Programmable many-core…”
Get full text

Accelerating design-technology co-development using neural compact modeling and data-driven SPICE simulation by Lee, Yongjeong, Lee, Seungsoo, Kim, Jeongyeol, Choi, Jungyun, Li, Zhaojie, Wu, Dehuang, Wang, Joddy

“…This paper proposes a new design-technology cooptimization framework that expedites circuit optimization by utilizing the neural compact modeling (NCM) and a…”
Get full text

SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation by Yu, Ziyang, Xu, Peng, Wang, Zixiao, Zhu, Binwu, Wang, Qipan, Lin, Yibo, Wang, Runsheng, Yu, Bei, Wong, Martin

“…The post-exposure bake (PEB) process is a critical step in semiconductor lithography, directly impacting resist profile accuracy and circuit pattern fidelity…”
Get full text

PiSPICE: Accelerating Post-Layout SPICE Simulation via Essential Parasitic Identification by Jin, Zhou, Li, Jing, Xin, Jian, Zhou, Tianjia, Wu, Xiao, Niu, Dan, Ye, Zuochang

“…As process nodes scale to more advanced technologies, post-layout simulations for integrated circuits have become increasingly complex, involving billions to…”
Get full text

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis by Li, Wenkai, Lu, Yao, Fang, Wenji, Wang, Jing, Zhang, Qijun, Xie, Zhiyao

“…Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout…”
Get full text

Generative Model Based Standard Cell Timing Library Characterization by Wu, Hao-Yu, Chang, Hsin-Tzu, Ding, Shiuan-Yun, Jiang, Iris Hui-Ru, Tsao, Benson, Wu, Vinson, Shih, Wei-Kai

“…Accurate cell timing characterization is essential, on which static timing analysis relies to verify timing performance and ensure design robustness across…”
Get full text

Self-Attention to Operator Learning-based 3D-IC Thermal Simulation by Huang, Zhen, Wang, Hong, Yang, Wenkai, Tang, Muxi, Xie, Depeng, Lin, Ting-Jung, Zhang, Yu, Xing, Wei W., He, Lei

“…Thermal management in 3D ICs is increasingly challenging due to higher power densities. Traditional PDESolving based methods, while accurate, are too slow for…”
Get full text

INSIGHT: A Universal Neural Simulator Framework for Analog Circuits with Autoregressive Transformers by Poddar, Souradip, Oh, Youngmin, Lai, Yao, Zhu, Hanqing, Hwang, Bosun, Pan, David Z.

“…The compute-intensive nature of SPICE simulations hinders effective analog design automation. This paper introduces INSIGHT, a data-efficient, adaptive,…”
Get full text