Search Results - "Hardware Electronic design automation Physical design (EDA) Partitioning and floorplanning"

Lightweight Structural Choices Operator for Technology Mapping by Grosnit, Antoine, Zimmer, Matthieu, Tutunov, Rasul, Li, Xing, Chen, Lei, Yang, Fan, Yuan, Mingxuan, Bou-Ammar, Haitham

“…Technology mapping quality heavily depends on the subject graph structure. To overcome structural biases, operators construct choice nodes to enable mappings with improved node and level counts…”
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Power/Ground Mesh Area Optimization Using Multigrid-Based Technique by Wang, Kai, Marek-Sadowska, Malgorzata

“…In this paper, we present a novel multigrid-based technique for power/ground mesh area optimization subject to reliability constraints…”
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Joint design-time and post-silicon optimization for digitally tuned analog circuits by Wei Yao, Yiyu Shi, Lei He, Pamarti, S.

“… In this paper we formulate the co-optimization problem for digitally tuned analog circuits to optimize the parametric yield, subject to power and area constraints…”
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Optimal clustering for delay minimization by Rajaraman, Rajmohan, Wong, D. F.

“…This paper addresses the problem of circuit clustering for delay minimization, subject to capacity constraints…”
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Technology migration techniques for simplified layouts with restrictive design rules by Tang, Xiaoping, Yuan, Xin

“…) with Restrictive Design Rules (RDRs) on each layout object (i.e., it must be placed on a set of grids subject to a set of ground rules…”
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Post-routing redundant via insertion and line end extension with via density consideration by Lee, Kuang-Yao, Wang, Ting-Chi, Chao, Kai-Yuan

“…Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due…”
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A technology independent block extraction algorithm by Luellau, F., Hoepken, T., Barke, E.

“… The algorithm is fully technology independent. The size of the blocks is not subject to any restrictions…”
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