Suchergebnisse - "Hardware Electronic design automation Logic synthesis Circuit optimization"

Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization von Liu, Meng-Yun, Lai, Yu-Cheng, Mak, Wai-Kei, Wang, Ting-Chi

“… bits. To maximize the FF merging rate (and hence to minimize the final amount of clock sinks), our approach will first perform aggressive FF merging subject to timing constraints …”
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A computing origami: folding streams in FPGAs von Hagiescu, Andrei, Wong, Weng-Fai, Bacon, David F., Rabbah, Rodric

“… Stream processing represents an important class of applications that spans telecommunications, multimedia and the Internet. The implementation of streaming …”
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Fast power/ground network optimization based on equivalent circuit modeling von Tan, X.-D. Sheldon, Shi, C.-J. Richard

“… This paper presents an efficient algorithm for optimizing the area of power or ground networks in integrated circuits subject to the reliability constraints …”
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Power/Ground Mesh Area Optimization Using Multigrid-Based Technique von Wang, Kai, Marek-Sadowska, Malgorzata

“… In this paper, we present a novel multigrid-based technique for power/ground mesh area optimization subject to reliability constraints …”
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Clock gating for power optimization in ASIC design cycle theory & practice von S, Jairam, Rao, Madhusudan, Srinivas, Jithendra, Vishwanath, Parimala, H, Udayakumar, Rao, Jagdish

“… We show that over 30% power savings in dynamic power can be achieved through this methodology subject to application scenarios of the design …”
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Post-routing redundant via insertion and line end extension with via density consideration von Lee, Kuang-Yao, Wang, Ting-Chi, Chao, Kai-Yuan

“… Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due …”
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Architectural synthesis of performance-driven multipliers with accumulator interleaving von Ghosh, Debabrata, Nandy, S. K., Sadayappan, P., Parthasarathy, K.

“… VLSI multipliers assume different characteristics in terms of latency, throughput and area for different target applications. This paper proposes a methodology …”
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Electrical optimization of PLAs von Hedlund, Kye S.

“… Algorithms are presented for: a) minimization of delay through the PLA b) minimization of power consumption subject to a bound on maximum delay …”
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