Výsledky vyhledávání - "Hardware Electronic design automation Logic synthesis Circuit optimization"

Scalable Optimal Layout Synthesis for NISQ Quantum Processors Autor Lin, Wan-Hsuan, Kimko, Jason, Tan, Bochen, Bjorner, Nikolaj, Cong, Jason

“…Due to its effect on the success rate of a quantum circuit, quantum layout synthesis is a crucial step for circuit compilation. As such, having a layout…”
Získat plný text

An Efficient Algorithm for Sparse Quantum State Preparation Autor Gleinig, Niels, Hoefler, Torsten

“…Generating quantum circuits that prepare specific states is an essential part of quantum compilation. Algorithms that solve this problem for general states…”
Získat plný text

Atomique: A Quantum Compiler for Reconfigurable Neutral Atom Arrays Autor Wang, Hanrui, Liu, Pengyu, Tan, Daniel Bochen, Liu, Yilian, Gu, Jiaqi, Pan, David Z., Cong, Jason, Acar, Umut A., Han, Song

“…The neutral atom array has gained prominence in quantum computing for its scalability and operation fidelity. Previous works focus on fixed atom arrays (FAAs)…”
Získat plný text

Tetris: A Compilation Framework for VQA Applications in Quantum Computing Autor Jin, Yuwei, Li, Zirui, Hua, Fei, Hao, Tianyi, Zhou, Huiyang, Huang, Yipeng, Zhang, Eddy Z.

“…Quantum computing has shown promise in solving complex problems by leveraging the principles of superposition and entanglement. Variational quantum algorithms…”
Získat plný text

How Good Is Your Verilog RTL Code? A Quick Answer from Machine Learning Autor Sengupta, Prianka, Tyagi, Aakash, Chen, Yiran, Hu, Jiang

“…Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to…”
Získat plný text

Hybrid Gate-Pulse Model for Variational Quantum Algorithms Autor Liang, Zhiding, Song, Zhixin, Cheng, Jinglei, He, Zichang, Liu, Ji, Wang, Hanrui, Qin, Ruiyang, Wang, Yiru, Han, Song, Qian, Xuehai, Shi, Yiyu

“…Current quantum programs are mostly synthesized and compiled on the gate-level, where quantum circuits are composed of quantum gates. The gate-level workflow,…”
Získat plný text

Approximate Equivalence Checking of Noisy Quantum Circuits Autor Hong, Xin, Ying, Mingsheng, Feng, Yuan, Zhou, Xiangzhen, Li, Sanjiang

“…We study the fundamental design automation problem of equivalence checking in the NISQ (Noisy Intermediate-Scale Quantum) computing realm where quantum noise…”
Získat plný text

Hardware-Software Co-design for Distributed Quantum Computing Autor Liu, Ji, Zang, Allen, Suchara, Martin, Zhong, Tian, Hovland, Paul D

“…Distributed quantum computing (DQC) offers a pathway for scaling up quantum computing architectures beyond the confines of a single chip. Entanglement is a…”
Získat plný text

Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving Autor Shi, Zhengyuan, Tang, Tiebing, Zhu, Jiaying, Khan, Sadaf, Zhen, Hui-Ling, Yuan, Mingxuan, Chu, Zhufei, Xu, Qiang

“…The Circuit Satisfiability (CSAT) problem, a variant of the Boolean Satisfiability (SAT) problem, plays a critical role in integrated circuit design and…”
Získat plný text

Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision Autor Fu, Rongliang, Zhang, Ran, Zheng, Ziyang, Shi, Zhengyuan, Pu, Yuan, Huang, Junying, Xu, Qiang, Ho, Tsung-Yi

“…Hybrid optimization is an emerging approach in logic synthesis, focusing on applying diverse optimization methods to different parts of a logic circuit. This…”
Získat plný text

Local Bayesian Optimization For Analog Circuit Sizing Autor Touloupas, Konstantinos, Chouridis, Nikos, Sotiriadis, Paul P.

“…This paper proposes a Bayesian Optimization (BO) algorithm to handle large-scale analog circuit sizing. The proposed approach uses a number of separate…”
Získat plný text

E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis Autor Chen, Chen, Hu, Guangyu, Yu, Cunxi, Ma, Yuzhe, Zhang, Hongce

“…In technology mapping, the quality of the final implementation heavily relies on the circuit structure after technologyindependent optimization. Recent studies…”
Získat plný text

Efficient Rectification Signal Validation for Optimal Functional ECO Patch Generation Autor Tung, Tzu-Yu, Hsu, Yu-Ling, Huang, Shao-Lun, Huang, Chung-Yang Ric

“…Synthesis-based functional Engineering Change Order (ECO) algorithms, as classified in [1], are particularly effective for addressing functional bugs. These…”
Získat plný text

Logic Restructuring with Preserved Logic Blocks Autor Lee, Siang-Yun, Riener, Heinz, Richter, Sascha, Sood, Ankush

“…During technology mapping, complex cells such as adders and multiplexers are often available in the standard cell library, which helps improve the final PPA…”
Získat plný text

EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis Autor Tang, Ruofei, Zhu, Xuliang, Zhang, Xinyi, Chen, Lei, Li, Xing, Yuan, Mingxuan, Xu, Jianliang

“…Boolean decomposition is a powerful technique in logic synthesis that breaks down Boolean functions into simpler components. Decomposition-based logic…”
Získat plný text

From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees Autor Luo, Donger, Sun, Qi, Li, Xingheng, Zhuo, Cheng, Yu, Bei, Geng, Hao

“…The growing complexity of modern hardware has created vast design spaces that are difficult to explore efficiently. Current design space exploration (DSE)…”
Získat plný text

Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization Problems Autor Qian, Yu, Huang, Xianmin, Wang, Ranran, Yang, Zeyu, Zhou, Min, Kampfe, Thomas, Zhuo, Cheng, Yin, Xunzhao

“…Combinatorial optimization problems (COPs) are crucial in many applications but are computationally demanding. Traditional Ising annealers address COPs by…”
Získat plný text

Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard Cells Autor Ahn, Jaehoon, Kim, Taewhan

“…With the continued scaling of VLSI technology beyond 3 nm, a consistent demand for layout reduction in standard cells has been made. CFET (Complementary-FET)…”
Získat plný text

A Fast, Iterative Clock Skew Scheduling Algorithm with Dynamic Sequential Graph Extraction Autor Chen, Shijian, Qiu, Yihang, Xie, Biwei, Chen, Mingyu, Li, Xingquan

“…Clock skew scheduling (CSS) is a well-known technique that improves design timing slack by adjusting clock latency to flipflops. CSS requires obtaining timing…”
Získat plný text

Harrow: Synthesis of Optical Logic Circuits via Harmonic Mean and Integer Partition Autor Liang, Jun-Wei, Jiang, Iris Hui-Ru, Chiu, Kai-Hsiang

“…With the advancement of high-speed and energyefficient optical interconnect and computation, photonic integrated circuits (PICs) have become a promising…”
Získat plný text