Search Results - "Computer systems organization Architectures Serial architectures Pipeline computing"

Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters by Cavalcante, Matheus, Wuthrich, Domenic, Perotti, Matteo, Riedel, Samuel, Benini, Luca

“…While parallel architectures based on clusters of Processing Elements (PEs) sharing L1 memory are widespread, there is no consensus on how lean their PE should…”
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Buffer Prospector: Discovering and Exploiting Untapped Buffer Resources in Many-Core DNN Accelerators by Wei, Yuchen, Cai, Jingwei, Gao, Mingyu, Peng, Sen, Wu, Zuotong, Shi, Guiming, Ma, Kaisheng

“…In large-scale DNN inference accelerators, the many-core architecture has emerged as a predominant design, with layer-pipeline (LP) mapping being a mainstream…”
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Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation by Tagata, Hiroto, Sato, Takashi, Awano, Hiromitsu

“…Deep neural networks (DNNs) have been widely applied in our society, yet reducing power consumption due to large-scale matrix computations remains a critical…”
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UDP: Utility-Driven Fetch Directed Instruction Prefetching by Oh, Surim, Xu, Mingsheng, Khan, Tanvir Ahmed, Kasikci, Baris, Litz, Heiner

“…Datacenter applications exhibit large instruction footprints causing significant instruction cache misses and, as a result, frontend stalls. To address this…”
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Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution by Bera, Rahul, Ranganathan, Adithya, Rakshit, Joydeep, Mahto, Sujit, Nori, Anant V., Gaur, Jayesh, Olgun, Ataberk, Kanellopoulos, Konstantinos, Sadrosadati, Mohammad, Subramoney, Sreenivas, Mutlu, Onur

“…Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like…”
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Alternate Path Fetch by Deshmukh, Aniket, Cai, Lingzhe Chester, Patt, Yale N.

“…Modern out-of-order cores rely on a large instruction supply from the processor frontend to achieve high performance. This requires building wider pipelines…”
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Alternate Path μ-op Cache Prefetching by Singh, Sawan, Perais, Arthur, Jimborean, Alexandra, Ros, Alberto

“…Datacenter applications are well-known for their large code footprints. This has caused frontend design to evolve by implementing decoupled fetching and large…”
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Sparse-T: Hardware accelerator thread for unstructured sparse data processing by Vasireddy, Pranathi, Kavi, Krishna, Mehta, Gayatri

“…Sparse matrix-dense vector (SpMV) multiplication is inherent in most scientific, neural networks and machine learning algorithms. To efficiently exploit…”
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Bit-level Perceptron Prediction for Indirect Branches by Garza, Elba, Mirbagher-Ajorpaz, Samira, Khan, Tahsin Ahmad, Jimenez, Daniel A.

“…Modern software uses indirect branches for various purposes including, but not limited to, virtual method dispatch and implementation of switch statements…”
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AVM-BTB: Adaptive and Virtualized Multi-level Branch Target Buffer by Liu, Yunzhe, Li, Xinyu, Zhang, Tingting, Liu, Tianyi, Guo, Qi, Zhang, Fuxin, Wang, Jian

“…Branch Target Buffer (BTB) plays an important role in modern processors. It is used to identify branches in the instruction stream and predict branch targets…”
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PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis by Li, Rui, Berkley, Lincoln, Manohar, Rajit

“…Dynamically scheduled high-level synthesis (HLS) is an approach to HLS that maps programs into dataflow circuits. These circuits use distributed control for…”
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UpPipe: A Novel Pipeline Management on In-Memory Processors for RNA-seq Quantification by Chen, Liang-Chi, Ho, Chien-Chung, Chang, Yuan-Hao

“…RNA sequence quantification is an important analysis method to measure transcript abundances. A key overhead in RNA-seq quantification is to map a set of RNA…”
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Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed by Liu, Chang, Lyu, Yongqiang, Wang, Haixia, Qiu, Pengfei, Ju, Dapeng, Qu, Gang, Wang, Dongsheng

“…Memory Disambiguation Unit (MDU) is widely used on modern processors to speculatively execute load instructions and improve pipeline performance. Given that…”
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Load value prediction via path-based address prediction: avoiding mispredictions due to conflicting stores by Sheikh, Rami, Cain, Harold W., Damodaran, Raguram

“…Current flagship processors excel at extracting instruction-level-parallelism (ILP) by forming large instruction windows. Even then, extracting ILP is…”
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MixPipe: Efficient Bidirectional Pipeline Parallelism for Training Large-Scale Models by Zhang, Weigang, Zhou, Biyu, Tang, Xuehai, Wang, Zhaoxing, Hu, Songlin

“…The rapid development of large-scale deep neural networks has put forward an urgent demand for the efficiency of parallel training. Recently, bidirectional…”
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SMT-COP: Defeating Side-Channel Attacks on Execution Units in SMT Processors by Townley, Daniel, Ponomarev, Dmitry

“…Recent advances in side-channel attacks put intoquestion the viability of Simultaneous Multithreading (SMT) architectures from the security standpoint. To…”
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Filter Caching for Free: The Untapped Potential of the Store-Buffer by Alves, Ricardo, Ros, Alberto, Black-Schaffer, David, Kaxiras, Stefanos

“…Modern processors contain store-buffers to allow stores to retire under a miss, thus hiding store-miss latency. The store-buffer needs to be large (for…”
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FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template by Choudhary, Niket K., Wadhavkar, Salil V., Shah, Tanmay A., Mayukh, Hiran, Gandhi, Jayneel, Dwiel, Brandon H., Navada, Sandeep, Najaf-abadi, Hashem H., Rotenberg, Eric

“…A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides…”
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X-Layer: Building Composable Pipelined Dataflows for Low-Rank Convolutions by Vedula, Naveen, Hojabr, Reza, Khonsari, Ahmad, Shriraman, Arrvindh

“…Prior research in hardware accelerators has largely focused on spatial convolutions (CONV). However, state-of-the-art DNNs employ low-rank convolutions…”
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Pipelining a triggered processing element by Repetti, Thomas J., Cerqueira, João P., Kim, Martha A., Seok, Mingoo

“…Programmable spatial architectures composed of ensembles of autonomous fixed-ISA processing elements offer a compelling design point between the flexibility of…”
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