Search Results - "Computer systems organization Architectures Parallel architectures Very long instruction word"

Automated Generation of Decoders for Irregular Instruction Sets Using Information-Theoretic Decision Tree Construction Algorithms by Tadros, Lillian

“…Instruction decoders are indispensable components of the System-on-Chip design flow and major constituents of instruction set simulators and processor…”
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Bit-level Perceptron Prediction for Indirect Branches by Garza, Elba, Mirbagher-Ajorpaz, Samira, Khan, Tahsin Ahmad, Jimenez, Daniel A.

“…Modern software uses indirect branches for various purposes including, but not limited to, virtual method dispatch and implementation of switch statements…”
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JouleTrack: a web based tool for software energy profiling by Sinha, Amit, Chandrakasan, Anantha P.

“…A software energy estimation methodology is presented that avoids explicit characterization of instruction energy consumption and pre-dicts energy consumption…”
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Outer-loop vectorization - revisited for short SIMD architectures by Nuzman, Dorit, Zaks, Ayal

“…Vectorization has been an important method of using data-level parallelism to accelerate scientific workloads on vector machines such as Cray for the past…”
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ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory by Jaewoong Chung, Yen, Luke, Diestelhorst, Stephan, Pohlack, Martin, Hohmuth, Michael, Christie, David, Grossman, Dan

“…Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region…”
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Security as a new dimension in embedded system design by Kocher, Paul, Lee, Ruby, McGraw, Gary, Raghunathan, Anand

“…The growing number of instances of breaches in information security in the last few years has created a compelling case for efforts towards secure electronic…”
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Cooperative cache scrubbing by Sartor, Jennifer B., Heirman, Wim, Blackburn, Stephen M., Eeckhout, Lieven, McKinley, Kathryn S.

“…Managing the limited resources of power and memory bandwidth while improving performance on multicore hardware is challenging. In particular, more cores demand…”
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SHRINK: Reducing the ISA complexity via instruction recycling by Lopes, Bruno Cardoso, Auler, Rafael, Ramos, Luiz, Borin, Edson, Azevedo, Rodolfo

“…Microprocessor manufacturers typically keep old instruction sets in modern processors to ensure backward compatibility with legacy software. The introduction…”
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Word level feature discovery to enhance quality of assertion mining by Liu, Lingyi, Lin, Chen-Hsuan, Vasudevan, Shobha

“…Automatic assertion generation methodologies based on machine learning generate assertions at bit level. These bit level assertions are numerous, making them…”
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Aging-aware compiler-directed VLIW assignment for GPGPU architectures by Rahimi, Abbas, Benini, Luca, Gupta, Rajesh K.

“…Negative bias temperature instability (NBTI) adversely affects the reliability of a processor by introducing new delay-induced faults. However, the effect of…”
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Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description by Wagstaff, Harry, Gould, Miles, Franke, Björn, Topham, Nigel

“…Modern processor design tools integrate in their workflows generators for instruction set simulators (Iss) from architecture descriptions. Whilst these…”
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Execution-based prediction using speculative slices by Zilles, Craig, Sohi, Gurindar

“…A relatively small set of static instructions has significant leverage on program execution performance. These problem instructions contribute a…”
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Tutorial: Introduction to the AMD Versal ACAP Adaptable Intelligent Engine and to its Programming Model by Ruiz Noguera, Mario Daniel, McCabe, Cathal

“…This tutorial introduces the Adaptable Intelligent Engine (AIE), a new type of compute element in the latest AMD technology. The AI Engines are a tiled array…”
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A new SBST algorithm for testing the register file of VLIW processors by Sabena, Davide, Reorda, Matteo Sonza, Sterpone, Luca

“…Feature size reduction drastically influences permanent faults occurrence in nanometer technology devices. Among the various test techniques, Software-Based…”
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A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture by Stripf, Timo, Koenig, Ralf, Becker, Juergen

“…Processor architectures that are capable to reconfigure their instruction set and instruction format dynamically at run time offer a new flexibility exploiting…”
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An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors by Clark, Nathan, Blome, Jason, Chu, Michael, Mahlke, Scott, Biles, Stuart, Flautner, Krisztian

“…Instruction set customization is an effective way to improve processor performance. Critical portions of applicationdata-flow graphs are collapsed for…”
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The TM3270 Media-Processor by van de Waerdt, Jan-Willem, Vassiliadis, Stamatis, Das, Sanjeev, Mirolo, Sebastian, Yen, Chris, Zhong, Bill, Basto, Carlos, van Itegem, Jean-Paul, Amirtharaj, Dinesh, Kalra, Kulbhushan, Rodriguez, Pedro, van Antwerpen, Hans

“…We present the TM3270 media-processor, the latest TriMedia VLIW processor, tuned to address the performance demands of standard definition video processing,…”
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Development of Fedora Linux Distribution for RISC-V (RV64G) Architecture by Billa, Surendra, Badar, Arif, Jadhav, Rushikesh, Sonawane, Yogeshwar, Wandhekar, Sanjay

“…The rapid evolution of the RISC-V architecture presents both opportunities and challenges, particularly for systems lacking support for compressed instructions…”
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An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures by Balensiefer, Steven, Kregor-Stickles, Lucas, Oskin, Mark

“…The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the…”
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Compiler-Directed Instruction Duplication for Soft Error Detection by Hu, Jie S., Li, Feihui, Degalahal, Vijay, Kandemir, Mahmut, Vijaykrishnan, N., Irwin, Mary J.

“…In this work, we experiment with complier-directed instruction duplication to detect soft errors in VLIW datapaths. Inthe proposed approach, the compiler…”
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