Search Results - "Computer system organization Architectures Other architecture Reconfigurable computing"

DRISA: a DRAM-based Reconfigurable In-Situ Accelerator by Li, Shuangchen, Niu, Dimin, Malladi, Krishna T., Zheng, Hongzhong, Brennan, Bob, Xie, Yuan

“…Data movement between the processing units and the memory in traditional von Neumann architecture is creating the "memory wall" problem. To bridge the gap, two…”
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Maximizing CNN accelerator efficiency through resource partitioning by Yongming Shen, Ferdman, Michael, Milder, Peter

“…Convolutional neural networks (CNNs) are revolutionizing machine learning, but they present significant computational challenges. Recently, many FPGA-based…”
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Stream-dataflow acceleration by Nowatzki, Tony, Gangadhar, Vinay, Ardalani, Newsha, Sankaralingam, Karthikeyan

“…Demand for low-power data processing hardware continues to rise inexorably. Existing programmable and "general purpose" solutions (eg. SIMD, GPGPUs) are…”
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Understanding and optimizing asynchronous low-precision stochastic gradient descent by De Sa, Christopher, Feldman, Matthew, Re, Christopher, Olukotun, Kunle

“…Stochastic gradient descent (SGD) is one of the most popular numerical algorithms used in machine learning and other domains. Since this is likely to continue…”
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Qubit Mapping for Reconfigurable Atom Arrays by Tan, Bochen, Bluvstein, Dolev, Lukin, Mikhail D., Cong, Jason

“…Because of the largest number of qubits available, and the massive parallel execution of entangling two-qubit gates, atom arrays is a promising platform for…”
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Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks by Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong

“…With the recent advancement of multilayer convolutional neural networks (CNN), deep learning has achieved amazing success in many areas, especially in visual…”
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SODA: Stencil with Optimized Dataflow Architecture by Chi, Yuze, Cong, Jason, Wei, Peng, Zhou, Peipei

“…Stencil computation is one of the most important kernels in many application domains such as image processing, solving partial differential equations, and…”
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TGPA: Tile-Grained Pipeline Architecture for Low Latency CNN Inference by Wei, Xuechao, Liang, Yun, Li, Xiuhong, Yu, Cody Hao, Zhang, Peng, Cong, Jason

“…FPGAs are more and more widely used as reconfigurable hardware accelerators for applications leveraging convolutional neural networks (CNNs) in recent years…”
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MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition by Qin, Yubin, Wang, Yang, Zhao, Zhiren, Yang, Xiaolong, Zhou, Yang, Wei, Shaojun, Hu, Yang, Yin, Shouyi

“…Large language models (LLMs) have been showing surprising performance in processing language tasks, bringing a new prevalence to deploy LLM from cloud to edge…”
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Hardware-Aware Machine Learning: Modeling and Optimization by Marculescu, Diana, Stamoulis, Dimitrios, Cai, Ermao

“…Recent breakthroughs in Machine Learning (ML) applications, and especially in Deep Learning (DL), have made DL models a key component in almost every modern…”
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Map-and-Conquer: Energy-Efficient Mapping of Dynamic Neural Nets onto Heterogeneous MPSoCs by Bouzidi, Halima, Odema, Mohanad, Ouarnoughi, Hamza, Niar, Smail, Al Faruque, Mohammad Abdullah

“…Heterogeneous MPSoCs comprise diverse processing units of varying compute capabilities. To date, the mapping strategies of neural networks (NNs) onto such…”
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ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions by Petrolo, Vincenzo, Guella, Flavia, Caon, Michele, Schiavone, Pasquale Davide, Masera, Guido, Martina, Maurizio

“…Modern data-driven applications expose limitations of von Neumann architectures-extensive data movement, low throughput, and poor energy efficiency…”
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A Memory-Efficient LLM Accelerator with Q-K Correlation Prediction using Cluster-Based Associative Array for Selective KV Accessing by Zhou, Zikang, Chen, Kaiqi, Duan, Xuyang, Han, Jun

“…Attention-based LLMs excel in text generation but face redundant computations in autoregressive token generation. While KV cache mitigates this, it introduces…”
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Supporting Register-based Addressing Modes for in-DRAM PIM ISAs by Kim, Seok Young, Choi, Byung Ho, Kang, Seokwon, Park, Yongjun, Kim, Seon Wook

“…Processing-in-Memory architecture presents a promising solution to alleviate the data movement bottleneck that arises from transferring data between memory and…”
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HH-PIM: Dynamic Optimization of Power and Performance with Heterogeneous-Hybrid PIM for Edge AI Devices by Jeon, Sangmin, Lee, Kangju, Lee, Kyeongwon, Lee, Woojoo

“…Processing-in-Memory (PIM) architectures offer promising solutions for efficiently handling AI applications in energy-constrained edge environments. While…”
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HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design by Luan, Xinya, Lin, Zhe, Shi, Kai, Zhai, Jianwang, Zhao, Kang

“…Singular value decomposition (SVD) is a matrix factorization technique widely used in signal processing and recommendation systems, etc. In general, the time…”
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Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores by Colagrande, Luca, Benini, Luca

“…To meet the computational requirements of modern workloads under tight energy constraints, general-purpose accelerator architectures have to integrate an…”
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RADiT: Redundancy-Aware Diffusion Transformer Acceleration Leveraging Timestep Similarity by Park, Youngjun, Kim, Sangyeon, Kim, Yeonggeon, Ji, Gisan, Ryu, Sungju

“…Diffusion Transformers (DiTs) have demonstrated unprecedented performance across various generative tasks including image and video generation. However, a…”
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Late Breaking Results: FPGen-3D: Automated Framework for 3D-FPGA Architecture Generation and Exploration by Youssef, Ismael, Hao, Cong Callie

“…In this work, we propose FPGen-3D, an automated framework for 3D field-programmable gate arrays (FPGA) architecture generation and exploration. FPGen-3D…”
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Buffer Prospector: Discovering and Exploiting Untapped Buffer Resources in Many-Core DNN Accelerators by Wei, Yuchen, Cai, Jingwei, Gao, Mingyu, Peng, Sen, Wu, Zuotong, Shi, Guiming, Ma, Kaisheng

“…In large-scale DNN inference accelerators, the many-core architecture has emerged as a predominant design, with layer-pipeline (LP) mapping being a mainstream…”
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