Suchergebnisse - "Computer Science - Hardware Architecture"

VirtualSync+: Timing Optimization With Virtual Synchronization von Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann

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Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning von Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Gernot Heiser, Luca Benini

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An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA von Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham

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Reducing the memory usage of Lattice-Boltzmann schemes with a DWT-based compression von Flint, Clément, Helluy, Philippe

“… This paper presents a new solution to address the challenge of increasing memory usage in high-performance computing simulations of Lattice-Bolzmann or …”
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A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB von Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham

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A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion von Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham

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Triangel: A High-Performance, Accurate, Timely On-Chip Temporal Prefetcher von Ainsworth, Sam, Mukhanov, Lev

“… Temporal prefetching, where correlated pairs of addresses are logged and replayed on repeat accesses, has recently become viable in commercial designs. Arm's …”
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PIVOT- Input-aware Path Selection for Energy-efficient ViT Inference von Moitra, Abhishek, Bhattacharjee, Abhiroop, Panda, Priyadarshini

“… The attention module in vision transformers(ViTs) performs intricate spatial correlations, contributing significantly to accuracy and delay. It is thereby …”
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A Universal LiDAR SLAM Accelerator System on Low-Cost FPGA von Keisuke Sugiura, Hiroki Matsutani

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A low-overhead soft–hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems von Abderazek Ben Abdallah, Khanh N. Dang, Yuichi Okuyama, Michael Conrad Meyer

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NTT-PIM: Row-Centric Architecture and Mapping for Efficient Number-Theoretic Transform on PIM von Park, Jaewoo, Lee, Sugil, Lee, Jongeun

“… Recently DRAM-based PIMs (processing-in-memories) with unmodified cell arrays have demonstrated impressive performance for accelerating AI applications …”
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PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender von Li, Luyi, Huang, Jiayi, Lang, Feng, Wang, Zhongfeng

“… Cache side channel attacks are increasingly alarming in modern processors due to the recent emergence of Spectre and Meltdown attacks. A typical attack …”
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Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture von Aflalo, Noa, Eilam Yalon, Kvatinsky, Shahar

“… This paper experimentally demonstrates a near-crossbar memory logic technique called Pinatubo. Pinatubo, an acronym for Processing In Non-volatile memory …”
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The Case for Replication-Aware Memory-Error Protection in Disaggregated Memory von Volos, Haris

“… Disaggregated memory leverages recent technology advances in high-density, byte-addressable non-volatile memory and high-performance interconnects to provide a …”
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Unveiling the Real Performance of LPDDR5 Memories von Steiner, Lukas, Jung, Matthias, Huonker, Michael, Wehn, Norbert

“… LPDDR5 is the latest low-power DRAM standard and expected to be used in various application fields. The vendors have published promising peak bandwidths up to …”
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MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory von Riedel, Samuel, Cavalcante, Matheus, Andri, Renzo, Benini, Luca

“… Shared L1 memory clusters are a common architectural pattern (e.g., in GPGPUs) for building efficient and flexible multi-processing-element (PE) engines …”
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Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory von Perach, Ben, Ronen, Ronny, Kvatinsky, Shahar

“… Bulk-bitwise processing-in-memory (PIM), an emerging computational paradigm utilizing memory arrays as computational units, has been shown to benefit database …”
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A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI von Bauer, Heiner, Stolba, Marco, Scholze, Stefan, Walter, Dennis, Mayr, Christian, Oefelein, Alexander, Höppner, Sebastian, Scharfe, André, Schraut, Flo, Eisenreich, Holger

“… We present a low-power, energy efficient 32-bit RISC-V microprocessor unit (MCU) in 22 nm FD-SOI. It achieves ultra-low leakage,even at high temperatures, by …”
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A Low-Latency FFT-IFFT Cascade Architecture von Parhi, Keshab K

“… This paper addresses the design of a partly-parallel cascaded FFT-IFFT architecture that does not require any intermediate buffer. Folding can be used to …”
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Toward Taming the Overhead Monster for Data-Flow Integrity von Lang, Feng, Huang, Jiayi, Huang, Jeff, Hu, Jiang

“… Data-Flow Integrity (DFI) is a well-known approach to effectively detecting a wide range of software attacks. However, its real-world application has been …”
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