Search Results - "Applied computing Physical sciences and engineering Engineering"

Challenges on designing electrostatic discharge protection solutions for low power electronics by Liou, Juin J.

“…]. When a microchip or electronic system is subject to an ESD event, the huge ESD-induced current can likely damage the microchip and cause malfunction to the electronic system if the heat generated…”
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Fast power/ground network optimization based on equivalent circuit modeling by Tan, X.-D. Sheldon, Shi, C.-J. Richard

“…This paper presents an efficient algorithm for optimizing the area of power or ground networks in integrated circuits subject to the reliability constraints…”
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Efficient multiple-bit retention register assignment for power gated design: concept and algorithms by Chen, Yu-Guang, Shi, Yiyu, Lai, Kuan-Yu, Hui, Geng, Chang, Shih-Chieh

“…Retention registers have been widely used in power gated design to store data during sleep mode. Since they consume much larger area and power than normal…”
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Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations by Li, Min, Davoodi, Azadeh, Xie, Lin

“… which automatically generates the sensors subject to an area budget and available whitespace on the layout…”
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Multiple tunable constant multiplications: algorithms and applications by Aksoy, Levent, Costa, Eduardo, Flores, Paulo, Monteiro, José

“… for the multiplication of multiple constants by an input variable, has been the subject of great interest since the complexity of many digital signal processing (DSP…”
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Investigating the readability of state-based formal requirements specification languages by Zimmerman, Marc K., Lundqvist, Kristina, Leveson, Nancy

“…, the use of hierarchies, and transition perspective (going-to or coming-from). Subjects included computer scientists as well as aerospace engineers in an effort to determine whether background affects notational preferences…”
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Lattice QCD with domain decomposition on Intel® Xeon Phi™ co-processors by Heybrock, Simon, Joó, Bálint, Kalamkar, Dhiraj D., Smelyanskiy, Mikhail, Vaidyanathan, Karthikeyan, Wettig, Tilo, Dubey, Pradeep

“…The gap between the cost of moving data and the cost of computing continues to grow, making it ever harder to design iterative solvers on extreme-scale…”
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A new structural pattern matching algorithm for technology mapping by Zhao, Min, Sapatnekar, Sachin S.

“… The algorithm is based on a key observation that the matches for a node in a subject Boolean network are related to the matches for its children…”
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Delay-optimal technology mapping by DAG covering by Kukimoto, Yuji, Brayton, Robert K., Sawkar, Prashant

“… We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs…”
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Defect tolerant probabilistic design paradigm for nanotechnologies by Jacome, Margarida, He, Chen, de Veciana, Gustavo, Bijansky, Stephen

“…Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near…”
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A submodular optimization approach to controlled islanding under cascading failure by Liu, Zhipeng, Clark, Andrew, Lee, Phillip, Bushnell, Linda, Kirschen, Daniel, Poovendran, Radha

“…Cascading failures occur when the power system is subject to a significant disturbance, such as tripping one or more transmission lines…”
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A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs by Singh, Amit Kumar, Kumar, Akash, Srikanthan, Thambipillai

“…Modern embedded systems are based on Multiprocessor-Systems-on-Chip (MPSoCs) to meet the strict timing deadlines of multiple applications. MPSoC resources must…”
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A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis by Wang, Tianchen, Samal, Sandeep Kumar, Lim, Sung Kyu, Shi, Yiyu

“…Through-silicon vias (TSVs) are subject to thermal fatigue due to stress over time, no matter how small the stress…”
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ToPoliNano: nanoarchitectures design made real by Frache, S., Chiabrando, D., Graziano, M., Riente, F., Turvani, G., Zamboni, M.

“… Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools…”
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Communication Scheduling and Buslet Synthesis for Low-Interconnect HLS Designs by Tartaglione, Enzo, Dutt, Shantanu

“…Current nanoscale designs are highly interconnect dominated, taking about 70% of the chip area. Interconnects also consume significant dynamic power, and about…”
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Power/Ground Mesh Area Optimization Using Multigrid-Based Technique by Wang, Kai, Marek-Sadowska, Malgorzata

“…In this paper, we present a novel multigrid-based technique for power/ground mesh area optimization subject to reliability constraints…”
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Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics by Vijayakumar, Priyamvada, Narayanan, Pritish, Koren, Israel, Mani Krishna, C., Moritz, Csaba Andras

“… A bottom-up fabrication of nanoelectronic circuits is expected to be subject to various defects and identifying the types of defects that may occur during each step of a manufacturing pathway…”
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Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation by Chen, Chung-Ping, Chu, Chris C. N., Wong, D. F.

“… We present a fast and exact algorithm which can minimize total area subject to maximum delay bound…”
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Policy optimization for dynamic power management by Paleologo, G. A., Benini, L., Bogliolo, A., De Micheli, G.

“… Furthermore, we show that the fundamental problem of finding an optimal policy which maximizes the average performance level of a system, subject to a constraint on the power consumption…”
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Joint design-time and post-silicon optimization for digitally tuned analog circuits by Wei Yao, Yiyu Shi, Lei He, Pamarti, S.

“… In this paper we formulate the co-optimization problem for digitally tuned analog circuits to optimize the parametric yield, subject to power and area constraints…”
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