Výsledky vyhledávání - "Applied computing Physical sciences and engineering Engineering"

ChipletEM: Physics-Based 2.5D and 3D Chiplet Heterogeneous Integration Electromigration Signoff Tool Using Coupled Stress and Thermal Simulation Autor Sun, Zeyu, Tong, Weijie, Ma, Xiaoning, Cao, He, Liu, Jianyun, Li, Zhiqiang, Xu, Qinzhi

“…A review of recent studies on up-to-date IC shows that electromigration (EM) has become one of the major challenges for 2.5D and 3D chiplet heterogeneous…”
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How Good Is Your Verilog RTL Code? A Quick Answer from Machine Learning Autor Sengupta, Prianka, Tyagi, Aakash, Chen, Yiran, Hu, Jiang

“…Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to…”
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DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design Autor Liu, Ziyue, Li, Yixing, Hu, Jing, Yu, Xinling, Shiau, Shinyu, Ai, Xin, Zeng, Zhiyu, Zhang, Zheng

“…Thermal issue is a major concern in 3D integrated circuit (IC) design. Thermal optimization of 3D IC often requires massive expensive PDE simulations. Neural…”
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Local Bayesian Optimization For Analog Circuit Sizing Autor Touloupas, Konstantinos, Chouridis, Nikos, Sotiriadis, Paul P.

“…This paper proposes a Bayesian Optimization (BO) algorithm to handle large-scale analog circuit sizing. The proposed approach uses a number of separate…”
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E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis Autor Chen, Chen, Hu, Guangyu, Yu, Cunxi, Ma, Yuzhe, Zhang, Hongce

“…In technology mapping, the quality of the final implementation heavily relies on the circuit structure after technologyindependent optimization. Recent studies…”
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Invited: EDA for Heterogeneous Integration Autor Haque, Emad, Nalla, Pragnya, Sudarshan, Chetan Choppali, Yogi, Divya, Zhang, Hangyu, Chakrabarti, Chaitali, Chhabria, Vidya A., Harjani, Ramesh, Zhang, Jeff, Sapatnekar, Sachin S.

“…The advent of heterogeneous integration (HI) places new demands on EDA tooling. Building large systems requires (1) methods for chiplet disaggregation that map…”
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BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation Autor Yin, Jiaqi, Song, Zhan, Chen, Chen, Hu, Qihao, Yu, Cunxi

“…Boolean symbolic reasoning for gate-level netlists is a critical step in verification, logic and datapath synthesis, and hardware security. Specifically,…”
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2022 ICCAD CAD Contest Problem B: 3D Placement with D2D Vertical Connections Autor Hu, Kai-Shun, Lin, I-Jye, Huang, Yu-Hui, Chi, Hao-Yu, Wu, Yi-Hsuan, Shen, Chin-Fang Cindy

“…In the chiplet era, the benefits from multiple factors can be observed by splitting a large single die into multiple small dies. By having the multiple small…”
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X-SAT: An Efficient Circuit-Based SAT Solver Autor Qian, Yuhang, Chen, Zhihan, Zhang, Xindi, Cai, Shaowei

“…In modern digital circuit design, verifying the equivalence of arithmetic circuits is a significant and challenging task. This paper introduces a new circuit…”
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DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters Autor Xie, Zhiyao, Li, Shiyu, Ma, Mingyuan, Chang, Chen-Chia, Pan, Jingyu, Chen, Yiran, Hu, Jiang

“…Accurate and efficient on-chip power modeling is crucial to runtime power, energy, and voltage management. Such power monitoring can be achieved by designing…”
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INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications Autor Lu, Yi-Chen, Guo, Zhizheng, Kunal, Kishor, Liang, Rongjian, Ren, Haoxing

“…Prior GPU-accelerated Static Timing Analysis (GPU-STA) works all struggle to find industrial adoption, primarily because they aim to build standalone timing…”
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Differentiable Net-Moving and Local Congestion Mitigation for Routability-Driven Global Placement Autor Li, Wenchao, Wu, Hongxi, Liu, Duanxiang, Li, Xingquan, Zhu, Wenxing

“…Routability-driven global placement is a major challenge in modern VLSI physical design, for which mitigating routing congestion is a critical approach. Cell…”
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YAP: Yield Modeling and Simulation for Advanced Packaging Autor Chen, Zhichao, Gupta, Puneet

“…Three-dimensional integration technologies present a promising path forward for extending Moore's law, facilitating high-density interconnects between chips…”
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A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs Autor Guo, Zizheng, Huang, Tsung-Wei, Lin, Yibo

“…Common path pessimism removal (CPPR) is imperative for eliminating redundant pessimism during static timing analysis (STA). However, turning on CPPR can…”
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GPU-accelerated Path-based Timing Analysis Autor Guo, Guannan, Huang, Tsung-Wei, Lin, Yibo, Wong, Martin

“…Path-based Analysis (PBA) is an important step in the design closure flow for reducing slack pessimism. However, PBA is extremely time-consuming. Recent years…”
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Applying GNNs to Timing Estimation at RTL : (Invited Paper) Autor Lopera, Daniela Sanchez, Ecker, Wolfgang

“…In the Electronic Design Automation (EDA) flow, signoff checks, such as timing analysis, are performed only after physical synthesis. Encountered timing…”
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Decoupling Analog Circuit Representation from Technology for Behavior-Centric Optimization Autor Li, Jintao, Zhi, Haochang, Xiao, Jiang, Zhu, Keren, Li, Yun

“…Analog IC design is mainly manual and implemented at the device level. A major reason is circuit behavior-extraction. Unlike its digital counterpart, analog IC…”
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Constraint Graph-based PCB Legalization Considering Dense, Heterogeneous, Irregular-Shaped, and Any-oriented Components Autor Ou, Chiao-Yu, Chen, Yan-Jen, Chang, Yao-Wen

“…In modern printed circuit board (PCB) designs, the increasing complexity poses more challenges for automatic placement. Existing PCB placement methods cannot…”
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Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability Optimization Autor Tsou, Chien-Hao, Lee, Zhu-Xun, Chang, Yao-Wen

“…This paper introduces an automated placement framework to optimize component positioning on modern printed circuit boards (PCBs), addressing challenges posed…”
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Clearance-Constrained PCB Global Placement with Heterogeneous Components Autor Chen, Yan-Jen, Huang, Wei-Kai, Tsai, Chung-Ting, Ou, Chiao-Yu, Chang, Yao-Wen

“…The complexity of design rules and intense time-to-market demands have made auto-placement tools essential for advanced printed circuit board (PCB) designs…”
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