Search Results - "Applied computing Physical sciences and engineering Electronics"

Late Breaking Results: Versatile 4:1 Multiplexer Using 1T1R RRAM Crossbar for High Speed In-Memory Computing by Vinodh Kumar, B, Kailath, Binsu J

“…This paper presents a high speed NAND based 4:1 Multiplexer (MUX) for various logic operations in a ResistiveRandom access memory crossbar structure. Compared…”
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Invited: EDA for Heterogeneous Integration by Haque, Emad, Nalla, Pragnya, Sudarshan, Chetan Choppali, Yogi, Divya, Zhang, Hangyu, Chakrabarti, Chaitali, Chhabria, Vidya A., Harjani, Ramesh, Zhang, Jeff, Sapatnekar, Sachin S.

“…The advent of heterogeneous integration (HI) places new demands on EDA tooling. Building large systems requires (1) methods for chiplet disaggregation that map…”
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Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits by Xunzhao Yin, Aziz, Ahmedullah, Nahas, Joseph, Datta, Suman, Gupta, Sumeet, Niemier, Michael, Xiaobo Sharon Hu

“…Numerous research efforts are targeting new devices that could continue performance scaling trends associated with Moore's Law and/or accomplish computational…”
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Energy characterization and instruction-level energy model of Intel's Xeon Phi processor by Shao, Yakun Sophia, Brooks, David

“…Intel's Xeon Phi is the first commercial many-core/multi-thread x86--based processor. Xeon Phi belongs to a new breed of high performance computing processors…”
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Bayesian Inference Based Robust Computing on Memristor Crossbar by Gao, Di, Huang, Qingrong, Zhang, Grace Li, Yin, Xunzhao, Li, Bing, Schlichtmann, Ulf, Zhuo, Cheng

“…Memristor based crossbars are a promising platform for neural network acceleration. To deploy a trained network model on a memristor crossbar, memristors need…”
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Low-Cost 7T-SRAM Compute-In-Memory Design based on Bit-Line Charge-Sharing based Analog-To-Digital Conversion by Lee, Kyeongho, Kim, Joonhyung, Park, Jongsun

“…Although compute-in-memory (CIM) is considered as one of the promising solutions to overcome memory wall problem, the variations in analog voltage computation…”
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Steep switching tunnel FET: a promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications by Liu, Huichu, Datta, Suman, Narayanan, Vijaykrishnan

“…Steep switching Tunnel FETs (TFET) can extend the supply voltage scaling with improved energy efficiency for both digital and analog/RF application. In this…”
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A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration by Lee, Kyeongho, Cheon, Sungsoo, Jo, Joongho, Choi, Woong, Park, Jongsun

“…This paper presents a charge-sharing based customized 8T SRAM in-memory computing (IMC) architecture. In the proposed IMC approach, the multiply-accumulate…”
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Understanding the Energy Consumption of Dynamic Random Access Memories by Vogelsang, T

“…Energy consumption has become a major constraint on the capabilities of computer systems. In large systems the energy consumed by Dynamic Random Access…”
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Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs by Liu, Liu, Kumar, Shubham, Thomann, Simon, Amrouch, Hussam, Hu, Xiaobo Sharon

“…Ternary content addressable memory (TCAM), widely used in network routers and high-associativity caches, is gaining popularity in machine learning and…”
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Memristor-based approximated computation by Li, Boxun, Shan, Yi, Hu, Miao, Wang, Yu, Chen, Yiran, Yang, Huazhong

“…The cessation of Moore's Law has limited further improvements in power efficiency. In recent years, the physical realization of the memristor has demonstrated…”
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Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges by Nibhanupudi, S. S. Teja, Oruganti, Sirish, Mathur, Rahul, Gupta, Nishant, Wang, Meizhi, Kulkarni, Jaydeep P.

“…Buried power rails and back-side power grids are promising technology-scaling boosters for advanced CMOS technology nodes. System-level evaluation of these…”
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Designing Energy-Efficient Decision Tree Memristor Crossbar Circuits using Binary Classification Graphs by Sinha, Pranav, Raj, Sunny

“…We propose a method to design in-memory, energy-efficient, and compact memristor crossbar circuits for implementing decision trees using flow-based computing…”
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Batteries and battery management systems for electric vehicles by Brandl, M., Gall, H., Wenger, M., Lorentz, V., Giegerich, M., Baronti, F., Fantechi, G., Fanucci, L., Roncella, R., Saletti, R., Saponara, S., Thaler, A., Cifrain, M., Prochazka, W.

“…The battery is a fundamental component of electric vehicles, which represent a step forward towards sustainable mobility. Lithium chemistry is now acknowledged…”
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Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias by Badr, Yasmine, Torres, Andres, Gupta, Puneet

“…Integrating Directed Self Assembly (DSA) and Multiple Patterning (MP) is an attractive option for printing contact and via layers for sub-7nm process nodes. In…”
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System-level Innovation for the Next Decade AI Performance, Power, Area with Co-optimization by Pan, Marcus

“…Power, performance, and area (PPA) are three key parameters in conventional system-on-chip design optimization. In post Moore's law era, system-level PPA…”
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MBus: An ultra-low power interconnect bus for next generation nanopower systems by Pannuto, Pat, Lee, Yoonmyung, Kuo, Ye-Sheng, Foo, ZhiYoong, Kempke, Benjamin, Kim, Gyouho, Dreslinski, Ronald G., Blaauw, David, Dutta, Prabal

“…As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will…”
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Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs by Pentapati, Sai Surya Kiran, Lim, Sung Kyu

“…In this paper, we present a novel heterogeneous design of Monolithic 3D ICs along with crucial design flow enhancements and better partitioning methods. The…”
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An Automated and Process-Portable Generator for Phase-Locked Loop by Wang, Zhongkai, Choi, Minsoo, Chang, Eric, Wright, John, Bae, Wooham, Du, Sijun, Liu, Zhaokai, Narevsky, Nathan, Schmidt, Colin, Biwas, Ayan, Nikolic, Borivoje, Alon, Elad

“…We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The…”
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Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks by Weize Yu, Uzun, Orhun Aras, Kose, Selcuk

“…Side-channel attacks have become a significant threat to the integrated circuit security. Circuit level techniques are proposed in this paper as a…”
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