Suchergebnisse - "Algorithm-hardware codesign"

Algorithm/Hardware Codesign for Real-Time On-Satellite CNN-Based Ship Detection in SAR Imagery von Yang, Geng, Lei, Jie, Xie, Weiying, Fang, Zhenman, Li, Yunsong, Wang, Jiaxuan, Zhang, Xin

“… In this article, we propose OSCAR-RT, the first end-to-end algorithm/hardware codesign framework for real-time on-satellite CNN-based SAR ship detection, which can simultaneously produce …”
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Improving Scalability of Mach-Zehnder Interferometer Based Photonic Computers via Algorithm-Hardware Codesign von On, Mehmet Berkay, Lee, Yun-Jhu, Srouji, Luis El, Abdelghany, Mahmoud, Yoo, S. J. Ben

“… Here, we explore two algorithm-hardware codesign approaches: continual learning and tensor-train decomposition to improve the scalability of the MZI-based photonic computers …”
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Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning von Fang, Haowen, Taylor, Brady, Li, Ziru, Mei, Zaidao, Li, Hai Helen, Qiu, Qinru

“… Neuromorphic computing and spiking neural networks (SNN) mimic the behavior of biological systems and have drawn interest for their potential to perform …”
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Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review von Shuvo, Md. Maruf Hossain, Islam, Syed Kamrul, Cheng, Jianlin, Morshed, Bashir I.

“… Successful integration of deep neural networks (DNNs) or deep learning (DL) has resulted in breakthroughs in many areas. However, deploying these highly …”
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An Algorithm-Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers von Fang, Chao, Zhou, Aojun, Wang, Zhongfeng

“… The Transformer has been an indispensable staple in deep learning. However, for real-life applications, it is very challenging to deploy efficient Transformers …”
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Algorithm-Hardware Codesign of Fast Parallel Round-Robin Arbiters von Zheng, Si Qing, Yang, Mei

“… As a basic building block of a switch scheduler, a fast and fair arbiter is critical to the efficiency of the scheduler, which is the key to the performance of …”
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Algorithm Hardware Codesign for High Performance Neuromorphic Computing von Fang, Haowen

“… Driven by the massive application of Internet of Things (IoT), embedded system and Cyber Physical System (CPS) etc., there is an increasing demand to apply …”
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Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design von Fang, Chao, Sun, Wei, Zhou, Aojun, Wang, Zhongfeng

“… Sparse training is one of the promising techniques to reduce the computational cost of DNNs while retaining high accuracy. In particular, N:M fine-grained …”
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An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization von Shao, Haikuo, Lu, Jinming, Wang, Meiqi, Wang, Zhongfeng

“… Transformers have achieved significant success in deep learning, and training Transformers efficiently on resource-constrained platforms has been attracting …”
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ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate Keypoint Detection of SIFT Algorithm von Fan, Zichen, Liu, Zheyu, Qu, Zheng, Qiao, Fei, Wei, Qi, Liu, Xinjun, Sun, Yinan, Xu, Shuzheng, Yang, Huazhong

“… The scale-invariant feature transform (SIFT) algorithm is still one of the most reliable image feature extraction methods. Despite its excellent robustness on …”
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HDReason: Algorithm-Hardware Codesign for Hyperdimensional Knowledge Graph Reasoning von Hanning Chen, Ni, Yang, Zakeri, Ali, Zou, Zhuowen, Sanggeon Yun, Wen, Fei, Khaleghi, Behnam, Narayan Srinivasa, Latapie, Hugo, Imani, Mohsen

“… In recent times, a plethora of hardware accelerators have been put forth for graph learning applications such as vertex classification and graph …”
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Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning von Fang, Haowen, Taylor, Brady, Li, Ziru, Zaidao Mei, Li, Hai, Qiu, Qinru

“… Neuromorphic computing and spiking neural networks (SNN) mimic the behavior of biological systems and have drawn interest for their potential to perform …”
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Accelerating ViT Inference on FPGA through Static and Dynamic Pruning von Parikh, Dhruv, Li, Shouyi, Zhang, Bingyi, Kannan, Rajgopal, Busart, Carl, Prasanna, Viktor

“… To address the above challenges, we propose a comprehensive algorithm-hardware codesign for accelerating ViT on FPGA through simultaneous pruning - combining static weight pruning and dynamic token pruning …”
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Towards spike-based machine intelligence with neuromorphic computing von Roy, Kaushik, Jaiswal, Akhilesh, Panda, Priyadarshini

“… Guided by brain-like ‘spiking’ computational frameworks, neuromorphic computing—brain-inspired computing for machine intelligence—promises to realize …”
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Biologically Switchable Volatility and Nonvolatility Toward Real Neurotransmitter Mediated Aqueous Reservoir Computing von Li, Zheng, Wu, Qing‐Qing, Wang, Yazhou, Lin, Peng, Xu, Jing‐Juan, Chen, Hong‐Yuan, Zhao, Wei‐Wei

“… The study on aqueous reservoir computing (RC) has just come into being. Nevertheless, aqueous RC still faces significant challenges. Recently, with the …”
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Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers von Loh, Johnson, Gemmeke, Tobias

“… ). In this work, we identify specific constraints to define common operating conditions, which guide the design of ECG accelerators in an algorithm-hardware codesign methodology …”
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Hardware-Algorithm Codesigned Low-Latency and Resource-Efficient OMP Accelerator for DOA Estimation on FPGA von Jiang, Ruichang, Ye, Wenbin

“… This article introduces an algorithm-hardware codesign optimized for low-latency and resource-efficient direction-of-arrival (DOA …”
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WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks von Yang, Chen, Meng, Yishuo, Xi, Jiawei, Xiang, Siwei, Wang, Jianfei, Mei, Kuizhi

“… In addition, an algorithm-hardware codesign method is proposed to efficiently and flexibly reduce the invalid computations led by the previous filter decomposition method …”
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KAM-Net: Kilobyte-Scale Ultralightweight Attention-Based Network for Glass Defect Detection With Algorithm/Hardware Co-Design von Zhao, Bingrui, Wang, Yaonan, Zhang, Hui, Liu, Jiaxuan, Zhang, Jinzhou

“… Then, we design an efficient algorithm/hardware codesign for KAM-Net on field programmable gate array (FPGA …”
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SPADE: Sparse Pillar-based 3D Object Detection Accelerator for Autonomous Driving von Lee, Minjae, Park, Seongmin, Kim, Hyungmin, Yoon, Minyong, Lee, Janghwan, Choi, Jun Won, Kim, Nam Sung, Kang, Mingu, Choi, Jungwook

“… In this paper, we propose SPADE, an algorithm-hardware codesign …”
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