Výsledky vyhledávání - "Algorithm-based verification"

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method Autor Yan, Aibin, Li, Zhixing, Gao, Zhongyu, Zhang, Jing, Huang, Zhengfeng, Ni, Tianming, Cui, Jie, Wang, Xiaolei, Girard, Patrick, Wen, Xiaoqing

“…In advanced CMOS technologies, integrated circuits are sensitive to multiple-node-upsets (MNUs) induced in harsh radiation environments. The existing…”
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LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments Autor Yan, Aibin, Li, Zhixing, Cui, Jie, Huang, Zhengfeng, Ni, Tianming, Girard, Patrick, Wen, Xiaoqing

“… In this article, a latch design protected against MNUs in the harsh radiation as well as an algorithm-based verification process is proposed…”
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Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement Autor Yan, Aibin, Hu, Changli, Li, Jing, Bai, Na, Huang, Zhengfeng, Ni, Tianming, Patrick, Girard, Wen, Xiaoqing

“…With the continuous advancement of CMOS technologies, soft errors, such as single-node upset (SNU) and double-node upset (DNU), caused by radiation in…”
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MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method Autor Aibin Yan, Zhixing Li, Zhongyu Gao, Jing Zhang, Zhengfeng Huang, Tianming Ni, Jie Cui, Xiaolei Wang, Patrick Girard, Xiaoqing Wen

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The Importance of Assuring Algorithm-based Verification Agents Autor Haugen, Odd Ivar

“…Safety verification is about creating trust and building confidence that a system is safe and conforms to the specified requirements. The term confidence means…”
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Algorithm-based Verification of Manufacturing Constraints for a Loadpath Reinforced Fabric Autor Gebhardt, Philipp, Bätge, Tjard, Türck, Eiko, Vietor, Thomas

“…Lightweight construction has become increasingly important in recent decades. The fundamental idea of lightweight design is not to save weight at any price,…”
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QtNURAV: A Robust Latch Design with Quintuple Node Upset Recovery and Algorithm based Verifications for Aerospace Applications Autor Yan, Aibin, Li, Jing, Bao, Han, Ni, Tianming, Huang, Zhengfeng, Liang, Bin, Girard, Patrick, Wen, Xiaoqing

“…With the continuous scaling of transistor feature sizes to the deep nano-scale, modern circuits have become increasingly sensitive to radiation-induced soft…”
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HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications Autor Guo, Xing, Zhang, Jiajia, Meng, Xu, Li, Zhenmin, Wen, Xiaoqing, Girard, Patrick, Liang, Bin, Yan, Aibin

“… design automation tools, we further propose an algorithm-based verification method that can automatically verify the node-upset-recovery of latches, which greatly simplifies the reliability-verification flow…”
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A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches Autor Xu, Hui, Qin, Xuewei, Ma, Ruijun, Liu, Chaoming, Zhu, Shuo, Wang, Jun, Liang, Huaguo

“…With the development of semiconductor technology, the shrinking of feature size in integrated circuits has made them more sensitive to multiple-node-upsets…”
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Cost-Optimized and Highly Robust Latches Providing Complete Quadruple-Node-Upset Tolerance and Recovery With Algorithm-Based Verifications Autor Yan, Aibin, Zhou, Chao, Ni, Tianming, Zhang, Jing, Cui, Jie, Huang, Zhengfeng, Girard, Patrick, Wen, Xiaoqing

“…With the aggressive shrinking of transistor feature sizes, nanoscale complementary metal oxide semiconductor (CMOS) circuits are becoming more vulnerable to…”
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Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications Autor Yan, Aibin, He, Yuting, Huang, Zhengfeng, Yan, Wenjie, Cui, Jie, Wang, Xiaolei, Ni, Tianming, Girard, Patrick, Wen, Xiaoqing

“…This article presents radiation-hardened flip-flop (FF) designs capable of tolerating soft errors, e.g., single-node upsets (SNUs), double-node upsets (DNUs)…”
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Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications Autor Aibin Yan, Yuting He, Zhengfeng Huang, Wenjie Yan, Jie Cui, Xiaolei Wang, Tianming Ni, Patrick Girard, Xiaoqing Wen

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A Low-Cost Quadruple-Node-Upset Tolerant Latch Design and Recovery Rate Optimization Algorithm Autor Huang, Zhengfeng, Jiang, Xinyu, Zhang, Yuqing, Wang, Xiaolei, Lu, Yingchun, Pan, Jun, Cheng, Fan, Wen, Xiaoqing, Yan, Aibin

“…With the continuous shrinking of nanoscale complementary metal-oxide-semiconductor (CMOS) technology, the critical charge of circuit nodes has significantly…”
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Fault-tolerant deep learning inference on CPU-GPU integrated edge devices with TEEs Autor Xu, Hongjian, Liao, Longlong, Liu, Xinqi, Chen, Shuguang, Chen, Jianguo, Liang, Zhixuan, Yu, Yuanlong

“… DarkneTF introduces algorithm-based verification to implement the FT deep learning inference…”
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Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies Autor Hao, Licai, Zhang, Xinyi, Dai, Chenghu, Zhao, Qiang, Lu, Wenjuan, Peng, Chunyu, Zhou, Yongliang, Lin, Zhiting, Wu, Xiulong

“…), QNU tolerant latch (QNUTL), and Latch Design and Algorithm-based Verification Protected against Multiple-Node-Upsets (LDAVPM…”
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NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization Autor Huang, Zhengfeng, Sun, Liting, Wang, Xu, Liang, Huaguo, Lu, Yingchun, Yan, Aibin, Pan, Jun, Wen, Xiaoqing

“…% reduction in power consumption compared to the latch design and algorithm-based verification protected against multiple-node upset (LDAVPM) latch and 51.44…”
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A High-Performance and High-Robustness Triple-Node-Upset Tolerant Latch Based on Redundant-Node Hardening Autor Zhao, Qiang, Liu, Qingyi, Zhang, Xinyi, Hao, Licai, Li, Xin, Zhang, Shengyue, Peng, Chunyu, Lin, Zhiting, Wu, Xiulong

“…In response to the issues of high cost, large overhead, and limited node fault tolerance in current latch hardening techniques, this article proposes a latch…”
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