Výsledky vyhľadávania - "ASIC implementations"

Securing the IoT ecosystem: ASIC-based hardware realization of Ascon lightweight cipher Autor Khan, Safiullah, Inayat, Kashif, Muslim, Fahad Bin, Shah, Yasir Ali, Atif Ur Rehman, Muhammad, Khalid, Ayesha, Imran, Malik, Abdusalomov, Akmalbek

“…The Internet of Things (IoT) nodes consist of sensors that collect environmental data and then perform data exchange with surrounding nodes and gateways…”
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An Estimator for the ASIC Footprint Area of Lightweight Cryptographic Algorithms Autor Martin, Honorio, Peris-Lopez, Pedro, Tapiador, Juan E., San Millan, Enrique

“…In resource-constrained devices such as RFID tags or implantable medical devices, algorithm designers need to make careful choices to ensure that their…”
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Physical Verification and Validation of the Digital Analog and Mixed-Signal Designs for the SCL 180nm CMOS Technology Autor Kolagatla, Venkata Reddy, Desalphine, Vivian

“…This paper provides a detailed overview of the essential tapeout checks required for successfully designing and tape-out of Digital, Analog, and Mixed-Signal…”
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A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications Autor Kolagatla, Venkata Reddy, Raveendran, Aneesh, Desalphine, Vivian

“…This paper presents the design, development and implementation of a novel and efficient Serial Peripheral Interface (SPI)-enabled Rivest-Shamir-Adleman (RSA)…”
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An Energy-and-Area-Efficient CNN Accelerator for Universal Powers-of-Two Quantization Autor Xia, Tian, Zhao, Boran, Ma, Jian, Fu, Gelin, Zhao, Wenzhe, Zheng, Nanning, Ren, Pengju

“…CNN model computation on edge devices is tightly restricted to the limited resource and power budgets, which motivates the low-bit quantization technology to…”
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Efficient Barrett Modular Multiplication Based on Toom-Cook Multiplication Autor Hao, Yue, Wang, Weijiang, Dang, Hua, Wang, Guiyu

“…The Toom-Cook multiplier (TCM) is the most suitable method for multiplying large integers with key widths typically employed in ECC or RSA due to its…”
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Extended Generalized Feistel Networks Using Matrix Representation to Propose a New Lightweight Block Cipher: Lilliput Autor Berger, Thierry P., Francq, Julien, Minier, Marine, Thomas, Gael

“…While Generalized Feistel Networks (GFNs) have been widely studied in the literature as a building block of a block cipher, we recall in this paper the results…”
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Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA Autor Potestad-Ordóñez, Francisco Eugenio, Valencia-Barrero, Manuel, Baena-Oliva, Carmen, Parra-Fernández, Pilar, Jiménez-Fernández, Carlos Jesús

“…One of the best methods to improve the security of cryptographic systems used to exchange sensitive information is to attack them to find their vulnerabilities…”
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Fully Digital Feedforward Background Calibration of Clock Skews for Sub-Sampling TIADCs Using the Polyphase Decomposition Autor Han Le Duc, Duc Minh Nguyen, Jabbour, Chadi, Desgreys, Patricia, Jamin, Olivier, Van Tam Nguyen

“…This paper presents a low-power fully digital clock skew feedforward background calibration technique in sub-sampling Time-Interleaved Analog-to-Digital…”
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A Fully Probabilistic Model for Sigmoid Approximation and Its Hardware- Efficient Implementation Autor Lu, Wenhao, Lu, Minshan, Zhang, Xiangfen, Lu, Zhongzhiguang, Sun, Miao, Dong, Boyi, Shu, Zhou

“…The sigmoid function is a representative activation function in shallow neural networks. Its hardware realization is challenging due to the complex exponential…”
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A novel modification and hardware implementation of the simplified AES algorithm for IoT applications Autor Pavan Nishith, V S S, Saha, Adriza, Patwari, Ashish

“…•Modified S-AES: Introduces a novel modification to the Simplified AES (S-AES) algorithm, utilizing Boolean logic for the substitution box (S-box), six rounds…”
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Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE Autor Studer, C, Benkeser, C, Belfanti, S, Quiting Huang

“…Turbo-decoding for the 3GPP-LTE (Long Term Evolution) wireless communication standard is among the most challenging tasks in terms of computational complexity…”
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All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition Autor Han Le Duc, Duc Minh Nguyen, Jabbour, Chadi, Graba, Tarik, Desgreys, Patricia, Jamin, Olivier, Van Tam Nguyen

“…This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs)…”
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Design of Parallel High Throughput Multi-mode Polar Codes Encoder Autor LIU Lihua,GUAN Wu,LIANG Liping

“…A 32 bit parallel concatenated multi-mode polar codes encoder structure is proposed to obtain a polar codes encoder which support multiple codes lengths and…”
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Deep Learning-Aided Belief Propagation Decoder for Polar Codes Autor Xu, Weihong, Tan, Xiaosi, Be'ery, Yair, Ueng, Yeong-Luh, Huang, Yongming, You, Xiaohu, Zhang, Chuan

“…This paper presents deep learning (DL) methods to optimize polar belief propagation (BP) decoding and concatenated LDPC-polar codes. First, two-dimensional…”
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A Cost-Efficient Router Architecture for HPC Inter-Connection Networks: Design and Implementation Autor Dai, Yi, Lu, Kai, Xiao, Liquan, Su, Jinshu

“…High-radix routers with lower latency and higher bandwidth play an increasingly important role in constructing large-scale interconnection networks such as…”
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Efficient Large-Width Montgomery Modular Multiplier Design Based on Toom–Cook-5 Autor Liu, Kuanhao, Wang, Xiaohua, Hao, Yue, Zhang, Jingqi, Wang, Weijiang

“…Toom–Cook-n multiplication is an efficient large-width multiplication algorithm based on a divide-and-conquer strategy, widely used in modular multiplication…”
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ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium Autor Mora-Gutierrez, J. M., Jimenez-Fernandez, C. J., Valencia-Barrero, M.

“…We are presenting the experimental measurements of the power consumption and the maximum frequency in an ASIC prototype of 12 versions of the Trivium cipher:…”
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Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder Autor Guohui Wang, Hao Shen, Yang Sun, Cavallaro, Joseph R., Vosoughi, Aida, Yuanbin Guo

“…To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high…”
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A novel multiplier-less convolution core for YOLO CNN ASIC implementation Autor Bagherzadeh, Shoorangiz, Daryanavard, Hassan, Semati, Mohammad Reza

“…The You Only Look Once (YOLO) algorithm has a good trade-off between accuracy and execution speed in object detection. The main bottleneck of execution speed…”
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