Suchergebnisse - "2023 60th ACM/IEEE Design Automation Conference (DAC)"

  1. 1

    Scalable Optimal Layout Synthesis for NISQ Quantum Processors von Lin, Wan-Hsuan, Kimko, Jason, Tan, Bochen, Bjorner, Nikolaj, Cong, Jason

    Veröffentlicht: IEEE 09.07.2023
    “… Due to its effect on the success rate of a quantum circuit, quantum layout synthesis is a crucial step for circuit compilation. As such, having a layout …”
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  2. 2

    Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks von Wu, Nan, Li, Yingjie, Hao, Cong, Dai, Steve, Yu, Cunxi, Xie, Yuan

    Veröffentlicht: IEEE 09.07.2023
    “… Reasoning high-level abstractions from bit-blasted Boolean networks (BNs) such as gate-level netlists can significantly benefit functional verification, logic …”
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  3. 3

    Chiplets: How Small is too Small? von Graening, Alexander, Pal, Saptadeep, Gupta, Puneet

    Veröffentlicht: IEEE 09.07.2023
    “… As chiplet systems increase in popularity, it is important to revisit the tradeoffs for converting a monolithic design to a chiplet system. Chip yield, …”
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  4. 4

    Compiler Optimization for Quantum Computing Using Reinforcement Learning von Quetschlich, Nils, Burgholzer, Lukas, Wille, Robert

    Veröffentlicht: IEEE 09.07.2023
    “… Any quantum computing application, once encoded as a quantum circuit, must be compiled before being executable on a quantum computer. Similar to classical …”
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  5. 5

    HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement von Iff, Patrick, Besta, Maciej, Cavalcante, Matheus, Fischer, Tim, Benini, Luca, Hoefler, Torsten

    Veröffentlicht: IEEE 09.07.2023
    “… 2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of …”
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  6. 6

    Restructure-Tolerant Timing Prediction via Multimodal Fusion von Wang, Ziyi, Liu, Siting, Pu, Yuan, Chen, Song, Ho, Tsung-Yi, Yu, Bei

    Veröffentlicht: IEEE 09.07.2023
    “… Fast and accurate pre-routing timing prediction is crucial in the very-large-scale integration (VLSI) design flow. Existing machine learning (ML)-assisted …”
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  7. 7

    Ising-CF: A Pathbreaking Collaborative Filtering Method Through Efficient Ising Machine Learning von Liu, Zhuo, Yang, Yunan, Pan, Zhenyu, Sharma, Anshujit, Hasan, Amit, Ding, Caiwen, Li, Ang, Huang, Michael, Geng, Tong

    Veröffentlicht: IEEE 09.07.2023
    “… Due to the Ising model's strong expressivity and Ising machines' unique computational power, it is highly desired if Ising-based learning can be used in …”
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  8. 8

    DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design von Liu, Ziyue, Li, Yixing, Hu, Jing, Yu, Xinling, Shiau, Shinyu, Ai, Xin, Zeng, Zhiyu, Zhang, Zheng

    Veröffentlicht: IEEE 09.07.2023
    “… Thermal issue is a major concern in 3D integrated circuit (IC) design. Thermal optimization of 3D IC often requires massive expensive PDE simulations. Neural …”
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  9. 9

    Graph Representation Learning for Microarchitecture Design Space Exploration von Yi, Xiaoling, Lu, Jialin, Xiong, Xiankui, Xu, Dong, Shang, Li, Yang, Fan

    Veröffentlicht: IEEE 09.07.2023
    “… Design optimization of modern microprocessors is a complex task due to the exponential growth of the design space. This work presents GRL-DSE, an automatic …”
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  10. 10

    Primer: Fast Private Transformer Inference on Encrypted Data von Zheng, Mengxin, Lou, Qian, Jiang, Lei

    Veröffentlicht: IEEE 09.07.2023
    “… It is increasingly important to enable privacy-preserving inference for cloud services based on Transformers. Post-quantum cryptographic techniques, e.g., …”
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  11. 11

    Hybrid Gate-Pulse Model for Variational Quantum Algorithms von Liang, Zhiding, Song, Zhixin, Cheng, Jinglei, He, Zichang, Liu, Ji, Wang, Hanrui, Qin, Ruiyang, Wang, Yiru, Han, Song, Qian, Xuehai, Shi, Yiyu

    Veröffentlicht: IEEE 09.07.2023
    “… Current quantum programs are mostly synthesized and compiled on the gate-level, where quantum circuits are composed of quantum gates. The gate-level workflow, …”
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  12. 12

    Privacy-Preserving DNN Training with Prefetched Meta-Keys on Heterogeneous Neural Network Accelerators von Li, Qiushi, Ren, Ju, Zhang, Yan, Song, Chengru, Liao, Yiqiao, Zhang, Yaoxue

    Veröffentlicht: IEEE 09.07.2023
    “… The embedded software may migrate the collected data to the server for DNN computation acceleration, which may compromise privacy. We propose a DNN computation …”
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  13. 13

    Efficient ILT via Multi-level Lithography Simulation von Sun, Shuyuan, Yang, Fan, Yu, Bei, Shang, Li, Zeng, Xuan

    Veröffentlicht: IEEE 09.07.2023
    “… Inverse Lithography Technology (ILT) is a widely investigated method to improve the yield of chip manufacturing. However, high computational complexity and …”
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  14. 14

    RL-MUL: Multiplier Design Optimization with Deep Reinforcement Learning von Zuo, Dongsheng, Ouyang, Yikang, Ma, Yuzhe

    Veröffentlicht: IEEE 09.07.2023
    “… Multiplication is a fundamental operation in many applications, and multipliers are widely adopted in various circuits. However, optimizing multipliers is …”
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    COSA:Co-Operative Systolic Arrays for Multi-head Attention Mechanism in Neural Network using Hybrid Data Reuse and Fusion Methodologies von Wang, Zhican, Wang, Gang, Jiang, Honglan, Xu, Ningyi, He, Guanghui

    Veröffentlicht: IEEE 09.07.2023
    “… Attention mechanism acceleration is becoming increasingly vital to achieve superior performance in deep learning tasks. Existing accelerators are commonly …”
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  16. 16

    RoSE: Robust Analog Circuit Parameter Optimization with Sampling-Efficient Reinforcement Learning von Gao, Jian, Cao, Weidong, Zhang, Xuan

    Veröffentlicht: IEEE 09.07.2023
    “… Design automation of analog circuits has been a long-standing challenge in the integrated circuit field. Recently, multiple methods based on learning or …”
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  17. 17

    Automating Constraint-Aware Datapath Optimization using E-Graphs von Coward, Samuel, Constantinides, George A., Drane, Theo

    Veröffentlicht: IEEE 09.07.2023
    “… Numerical hardware design requires aggressive optimization, where designers exploit branch constraints, creating optimization opportunities that are valid only …”
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    OmniBoost: Boosting Throughput of Heterogeneous Embedded Devices under Multi-DNN Workload von Karatzas, Andreas, Anagnostopoulos, Iraklis

    Veröffentlicht: IEEE 09.07.2023
    “… Modern Deep Neural Networks (DNNs) exhibit profound efficiency and accuracy properties. This has introduced application workloads that comprise of multiple DNN …”
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  19. 19

    Input-Aware Dynamic Timestep Spiking Neural Networks for Efficient In-Memory Computing von Li, Yuhang, Moitra, Abhishek, Geller, Tamar, Panda, Priyadarshini

    Veröffentlicht: IEEE 09.07.2023
    “… Spiking Neural Networks (SNNs) have recently attracted widespread research interest as an efficient alternative to traditional Artificial Neural Networks …”
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  20. 20

    HAIMA: A Hybrid SRAM and DRAM Accelerator-in-Memory Architecture for Transformer von Ding, Yan, Liu, Chubo, Duan, Mingxing, Chang, Wanli, Li, Keqin, Li, Kenli

    Veröffentlicht: IEEE 09.07.2023
    “… Through the attention mechanism, Transformer-based large-scale deep neural networks (LSDNNs) have demonstrated remarkable achievements in artificial …”
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