Výsledky vyhľadávania - abstraction techniques for modeling and verification
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Tools and Algorithms for the Construction and Analysis of Systems: 26th International Conference, TACAS 2020, Held As Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020, Dublin, Ireland, April 25-30, 2020, Proceedings, Part I
ISBN: 9783030451899, 3030451895Vydavateľské údaje: Cham Springer International Publishing AG 2020“… The papers are organized in topical sections as follows: Part I: Program verification; SAT and SMT; Timed and Dynamical Systems…”
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Tools and Algorithms for the Construction and Analysis of Systems: 26th International Conference, TACAS 2020, Held As Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020, Dublin, Ireland, April 25-30, 2020, Proceedings, Part II
ISBN: 9783030452360, 3030452360Vydavateľské údaje: Cham Springer International Publishing AG 2020“… The papers are organized in topical sections as follows: Part I: Program verification; SAT and SMT; Timed and Dynamical Systems…”
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Tools and Algorithms for the Construction and Analysis of Systems: 26th International Conference, TACAS 2020, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020, Dublin, Ireland, April 25–30, 2020, Proceedings, Part I
Vydavateľské údaje: Cham Springer Nature 2020“… The papers are organized in topical sections as follows: Part I: Program verification; SAT and SMT; Timed and Dynamical Systems…”
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Tools and Algorithms for the Construction and Analysis of Systems: 26th International Conference, TACAS 2020, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020, Dublin, Ireland, April 25–30, 2020, Proceedings, Part II
Vydavateľské údaje: Cham Springer Nature 2020“… The papers are organized in topical sections as follows: Part I: Program verification; SAT and SMT; Timed and Dynamical Systems…”
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Modeling and Analysis Technique for the Formal Verification of System-on-Chip Address Maps: Extended Abstract
ISSN: 1558-1101Vydavateľské údaje: EDAA 31.03.2025Vydané v Proceedings - Design, Automation, and Test in Europe Conference and Exhibition (31.03.2025)“…This paper proposes a modeling and analysis technique to verify SoC address maps…”
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A Formal Verification Method for the SOPC Software
ISSN: 0018-9529, 1558-1721Vydavateľské údaje: New York IEEE 01.06.2022Vydané v IEEE transactions on reliability (01.06.2022)“…System on programmable chip (SOPC) is a kind of system on a programmable chip. The system architecture is superior to the traditional design pattern. The…”
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Verifying Controllers With Vision-Based Perception Using Safe Approximate Abstractions
ISSN: 0278-0070, 1937-4151Vydavateľské údaje: New York IEEE 01.11.2022Vydané v IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2022)“…Fully formal verification of perception models is likely to remain challenging in the foreseeable future, and yet these models are being integrated into safety-critical control systems…”
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Possibilistic Cost Computation Tree Logic and Related Equivalence, Abstraction Technique
ISSN: 2169-3536, 2169-3536Vydavateľské údaje: Piscataway IEEE 01.01.2023Vydané v IEEE access (01.01.2023)“… As the verification model, furthermore, we investigated the syntax and semantics of possibilistic cost computation tree logic and utilized them to develop verification characteristics…”
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Compositional Abstraction and Safety Synthesis Using Overlapping Symbolic Models
ISSN: 0018-9286, 1558-2523, 1558-2523Vydavateľské údaje: IEEE 01.06.2018Vydané v IEEE transactions on automatic control (01.06.2018)“…In this paper, we develop a compositional approach to abstraction and safety synthesis for a general class of discrete-time nonlinear systems…”
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Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification
ISSN: 0278-0070, 1937-4151Vydavateľské údaje: New York IEEE 01.03.2017Vydané v IEEE transactions on computer-aided design of integrated circuits and systems (01.03.2017)“… UML and OCL are the de-facto specification languages for these tasks. They allow for capturing system properties and module behavior in an abstract but still formal fashion…”
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Automated verification and synthesis of stochastic hybrid systems: A survey
ISSN: 0005-1098, 1873-2836Vydavateľské údaje: Elsevier Ltd 01.12.2022Vydané v Automatica (Oxford) (01.12.2022)“…Stochastic hybrid systems have received significant attentions as a relevant modeling framework describing many systems, from engineering to the life sciences…”
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Specification and Verification Method of Parallel Hierarchical Timed Automata by Predicate Abstraction and Refinement
ISSN: 2169-3536, 2169-3536Vydavateľské údaje: Piscataway IEEE 01.01.2025Vydané v IEEE access (01.01.2025)“… The reduction technique of the state space for verifying embedded systems is crucial. On the other hand, Counterexample-Guided Abstraction Refinement (CEGAR…”
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Formal verification of a telerehabilitation system through an abstraction and refinement approach using Uppaal
ISSN: 1751-8806, 1751-8814Vydavateľské údaje: John Wiley & Sons, Inc 01.08.2023Vydané v IET software (01.08.2023)“…Formal methods are proven techniques that provide a rigorous mathematical basis to software development…”
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Efficient Symbolic Computation for Word-Level Abstraction From Combinational Circuits for Verification Over Finite Fields
ISSN: 0278-0070, 1937-4151Vydavateľské údaje: New York IEEE 01.07.2016Vydané v IEEE transactions on computer-aided design of integrated circuits and systems (01.07.2016)“…This paper introduces a technique to derive a word-level abstraction of the function implemented by a combinational logic circuit…”
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Superposition‐Based Abstractions for Quantum Data Encoding Verification
ISSN: 2632-8925, 2632-8925Vydavateľské údaje: Shenzhen John Wiley & Sons, Inc 01.01.2025Vydané v IET quantum communication (01.01.2025)“… The key idea to address scalability is the use of abstractions that reduce the verification problem to bit‐vector space…”
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Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification
ISSN: 0278-0070, 1937-4151Vydavateľské údaje: New York IEEE 01.08.2018Vydané v IEEE transactions on computer-aided design of integrated circuits and systems (01.08.2018)“… A general technique for scalable system-level verification is to construct an abstraction of SoC hardware and verify firmware/software using…”
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Decomposing Software Verification into Off-the-Shelf Components: An Application to CEGAR
ISSN: 1558-1225Vydavateľské údaje: ACM 01.05.2022Vydané v 2022 IEEE/ACM 44th International Conference on Software Engineering (ICSE) (01.05.2022)“…Techniques for software verification are typically realized as cohesive units of software with tightly coupled components…”
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Improving Formal Verification and Testing Techniques for Internet of Things and Smart Cities
ISSN: 1383-469X, 1572-8153Vydavateľské údaje: New York Springer US 01.04.2023Vydané v Mobile networks and applications (01.04.2023)“… On the first hand the techniques realted to formal verification are as follows. First, Abstraction consists in modelling a part of the system accurately and the other parts at high level…”
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Scenario Description Language for Automated Driving Systems: A Two Level Abstraction Approach
ISSN: 2577-1655Vydavateľské údaje: IEEE 11.10.2020Vydané v Conference proceedings - IEEE International Conference on Systems, Man, and Cybernetics (11.10.2020)“… Variety of scenario generation techniques have been advocated, including real-world data analysis, accident data analysis and via systems hazard analysis…”
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Set Partition and Trace Based Verification of Web Service Composition
ISSN: 1877-0509, 1877-0509Vydavateľské údaje: Elsevier B.V 2015Vydané v Procedia computer science (2015)“… Then, we propose a novel methodology for service interaction verification that uses service description (from WSDL…”
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